FPGA蓝牙控制电子琴.docx
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FPGA蓝牙控制电子琴.docx
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FPGA蓝牙控制电子琴
深圳大学考试答题纸
(以论文、报告等形式考核专用)
二○一四~二○一五学年度第2学期
课程编号
02
课程名称
数字系统设计
主讲教师
XXXX
评分
学号
XXXX
姓名
XXX
专业年级
XXXXX
教师评语:
题目:
蓝牙控制电子发生器
摘要:
基于Basys2设计平台而搭建的“谱曲软件在fpga上的实现”的系统,融入了蓝牙传输模块,VGA显示模块,以及安卓手机的app应用软件,完成了对课题的基本功能的实现。
谱曲软件由我校陈必红老师编写,通过输入“陈谱”,实现了对钢琴曲以及一般的乐曲的播放,软件界面如下
在界面的最下部分编写陈谱,再点击装入,就会出现美妙的乐曲
1、系统总流程
1.1系统总框图------------------------------------------------------------------------------------------------------3
1.2系统总框图介绍------------------------------------------------------------------------------------------------3
1.3设计中遇到的难点、舍弃。
---------------------------------------------------------------------------------3
2、蓝牙模块
1.1蓝牙模块波特率设置以及信号检测ASM图-------------------------------------------------------------4
1.2蓝牙主模块、ASM图---------------------------------------------------------------------------------------5,6
3、A模块(VGA模块由周玲同学编写实现)
4、分频器模块
4.1分频器模块的ASM图--------------------------------------------------------------------------------------------7
5、仿真--------------------------------------------------------------------------------------------------------------------8
6、资源利用以及布局布线后的时序--------------------------------------------------------------------------------9
7、开发板截图-----------------------------------------------------------------------------------------------------------10
8、代码一览-------------------------------------------------------------------------------------------------------------11
波特率设置模块以及检波
modulespeed_select_rx(clk,rst_n,bps_start,clk_bps);//
inputclk;
inputrst_n;
inputbps_start;
outputclk_bps;
reg[12:
0]cnt;
regclk_bps_r;
reg[2:
0]uart_ctrl;
always@(posedgeclkorposedgerst_n)
if(rst_n)
cnt<=13'd0;
elseif((cnt==5207)||!
bps_start)
cnt<=13'd0;
else
cnt<=cnt+1'b1;
always@(posedgeclkorposedgerst_n)begin
if(rst_n)
clk_bps_r<=1'b0;
elseif(cnt==2603)
clk_bps_r<=1'b1;
else
clk_bps_r<=1'b0;
end
assignclk_bps=clk_bps_r;
endmodule
inputclk;
inputrst_n;
inputrs232_rx;//
inputclk_bps;
outputbps_start;
output[7:
0]rx_data;
outputrx_int;output[9:
0]led;
outputreg[7:
0]led_new;
reg[9:
0]led;
regrs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3;
wireneg_rs232_rx;
always@(posedgeclkorposedgerst_n)begin
if(rst_n)begin
rs232_rx0<=1'b0;
rs232_rx1<=1'b0;
rs232_rx2<=1'b0;
rs232_rx3<=1'b0;
end
elsebegin
rs232_rx0<=rs232_rx;
rs232_rx1<=rs232_rx0;
rs232_rx2<=rs232_rx1;
rs232_rx3<=rs232_rx2;
end
end
assignneg_rs232_rx=rs232_rx3&rs232_rx2&~rs232_rx1&~rs232_rx0;
regbps_start_r;
reg[3:
0]num;
regrx_int;
always@(posedgeclkorposedgerst_n)
if(rst_n)begin
bps_start_r<=1'bz;
rx_int<=1'b0;
end
elseif(neg_rs232_rx)begin//
bps_start_r<=1'b1;
rx_int<=1'b1;
end
elseif(num==4'd12)begin
bps_start_r<=1'b0;
rx_int<=1'b0;
end
assignbps_start=bps_start_r;
reg[7:
0]rx_data_r;
reg[7:
0]rx_temp_data;
always@(posedgeclkorposedgerst_n)
if(rst_n)begin
led<=10'b000_0000000;
rx_temp_data<=8'd0;
num<=4'd0;
rx_data_r<=8'd0;
end
elseif(rx_int)begin
if(clk_bps)begin
num<=num+1'b1;
case(num)
4'd1:
rx_temp_data[0]<=rs232_rx;
4'd2:
rx_temp_data[1]<=rs232_rx;
4'd3:
rx_temp_data[2]<=rs232_rx;
4'd4:
rx_temp_data[3]<=rs232_rx;
4'd5:
rx_temp_data[4]<=rs232_rx;
4'd6:
rx_temp_data[5]<=rs232_rx;
4'd7:
rx_temp_data[6]<=rs232_rx;
4'd8:
rx_temp_data[7]<=rs232_rx;
default:
;
endcase
case(rx_temp_data)
8'b00000000:
led<=10'b000_0000000;
8'b00000001:
led<=10'b001_0000001;
8'b00000010:
led<=10'b001_0000010;
8'b00000011:
led<=10'b001_0000100;
8'b00000100:
led<=10'b001_0001000;
8'b00000101:
led<=10'b001_0010000;
8'b00000110:
led<=10'b001_0100000;
8'b00000111:
led<=10'b001_1000000;
8'b00001000:
led<=10'b010_0000001;
8'b00001001:
led<=10'b010_0000010;
8'b00001010:
led<=10'b010_0000100;
8'b00001011:
led<=10'b010_0001000;
8'b00001100:
led<=10'b010_0010000;
8'b00001101:
led<=10'b010_0100000;
8'b00001110:
led<=10'b010_1000000;
8'b00001111:
led<=10'b100_0000001;
8'b00010000:
led<=10'b100_0000010;
8'b00010001:
led<=10'b100_0000100;
8'b00010010:
led<=10'b100_0001000;
8'b00010011:
led<=10'b100_0010000;
8'b00010100:
led<=10'b100_0100000;
8'b00010101:
led<=10'b100_1000000;
endcase
led_new<=rx_temp_data;
end
elseif(num==4'd12)begin
num<=4'd0;//数据接收完毕
rx_data_r<=rx_temp_data;
end
end
assignrx_data=rx_data_r;
endmodule
modulesound(clk,rst_n,led_new,sound_out);
inputclk;
inputrst_n;
input[7:
0]led_new;
outputregsound_out;
reg[18:
0]fre;
reg[31:
0]value=0;
always@(posedgeclkorposedgerst_n)
begin
if(rst_n)
value<=1'b0;
else
begin
case(led_new)
8'd1:
fre<=18'd18898;
8'd2:
fre<=18'd21212;
8'd3:
fre<=18'd19515;
8'd4:
fre<=18'd25223;
8'd5:
fre<=18'd28315;
8'd6:
fre<=18'd31783;
8'd7:
fre<=18'd35674;
8'd8:
fre<=18'd37796;
8'd9:
fre<=18'd42424;
8'd10:
fre<=18'd47588;
8'd11:
fre<=18'd50451;
8'd12:
fre<=18'd56608;
8'd13:
fre<=18'd63566;
8'd14:
fre<=18'd71348;
8'd15:
fre<=18'd75592;
8'd16:
fre<=18'd84843;
8'd17:
fre<=18'd95177;
8'd18:
fre<=18'd100846;
8'd19:
fre<=18'd113259;
8'd20:
fre<=18'd127130;
8'd21:
fre<=18'd142680;
default:
fre<=18'd86;
endcase
value<=value+fre;
end
end
//--------------------------------------
always@(posedgeclkorposedgerst_n)
begin
if(rst_n)
sound_out<=1'b0;
else
begin
if(value<32'h7FFF_FFFF)
sound_out<=1'b0;
else
sound_out<=1'b1;
end
end
endmodule
仿真
FPGA开发的布局布线后的时序和资源利用报告
实验成功的开发板截图
最终主模块代码
moduletonetop(clk,clr,rxd,hsync,vsync,rgb_8bits,sound_out);
inputclk;
inputclr;
inputrxd;
outputhsync;
outputvsync;
output[7:
0]rgb_8bits;
outputsound_out;
wire[7:
0]led_new;
wire[9:
0]control;
wire[20:
0]tone;
sounds(.clk(clk),.rst_n(clr),.led_new(led_new),.sound_out(sound_out));
uart_topuut4(.clk(clk),.rst_n(clr),.rs232_rx(rxd),.led(control),.led_new(led_new));
keynauut1(.clr(clr),.clk(clk),.control(control),.tone(tone));
vgauut2(.clk(clk),.clr(clr),.tone(tone),.hsync(hsync),.vsync(vsync),.rgb_8bits(rgb_8bits));
Endmodule
分频器代码
modulesound(clk,rst_n,led_new,sound_out);
inputclk;
inputrst_n;
input[7:
0]led_new;
outputregsound_out;
reg[18:
0]fre;
//parameterFREQ_WORD=32'd44;//1KHz
reg[31:
0]value=0;
always@(posedgeclkorposedgerst_n)
begin
if(rst_n)
value<=1'b0;
else
begin
case(led_new)
8'd1:
fre<=18'd18898;
8'd2:
fre<=18'd21212;
8'd3:
fre<=18'd19515;
8'd4:
fre<=18'd25223;
8'd5:
fre<=18'd28315;
8'd6:
fre<=18'd31783;
8'd7:
fre<=18'd35674;
8'd8:
fre<=18'd37796;
8'd9:
fre<=18'd42424;
8'd10:
fre<=18'd47588;
8'd11:
fre<=18'd50451;
8'd12:
fre<=18'd56608;
8'd13:
fre<=18'd63566;
8'd14:
fre<=18'd71348;
8'd15:
fre<=18'd75592;
8'd16:
fre<=18'd84843;
8'd17:
fre<=18'd95177;
8'd18:
fre<=18'd100846;
8'd19:
fre<=18'd113259;
8'd20:
fre<=18'd127130;
8'd21:
fre<=18'd142680;
default:
fre<=18'd86;
endcase
value<=value+fre;
end
end
//--------------------------------------
always@(posedgeclkorposedgerst_n)
begin
if(rst_n)
sound_out<=1'b0;
else
begin
if(value<32'h7FFF_FFFF)
sound_out<=1'b0;
else
sound_out<=1'b1;
end
end
endmodule
蓝牙主模块代码
`timescale1ns/1ps
moduleuart_top(clk,rst_n,rs232_rx,led,led_new);
inputclk;//时钟信号50M
inputrst_n;//复位信号,低有效
inputrs232_rx;//数据输入信号//数据输出信号
output[9:
0]led;
output[7:
0]led_new;
wire[7:
0]led_new;
wirebps_start1,bps_start2;//
wireclk_bps1,clk_bps2;
wire[7:
0]rx_data;//接收数据存储器,用来存储接收到的数据,直到下一个数据接收
wirerx_int;//接收数据中断信号,接收过程中一直为高,
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////子模块端口申明///////////////////////////////////
speed_select_rxspeed_rx(//数据接收波特率选择模块
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start1),
.clk_bps(clk_bps1)
);
uart_rxuart_rx(//数据接收模块
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start1),
.clk_bps(clk_bps1),
.rs232_rx(rs232_rx),
.rx_data(rx_data),
.rx_int(rx_int),
.led(led),
.led_new(led_new)
);
Endmodule
波特率设置以及信号检测代码
modulespeed_select_rx(clk,rst_n,bps_start,clk_bps);//波特率设定
inputclk;//50M时钟
inputrst_n;//复位信号
inputbps_start;//接收到信号以后,波特率时钟信号置位,当接收到uart_rx传来的信号以后,模块开始运行
outputclk_bps;//接收数据中间采样点,
//`defineBPS_PARA5207;//9600波特率分频计数值
//`defineBPS_PARA_22603;//计数一半时采样
reg[12:
0]cnt;//分频计数器
regclk_bps_r;//波特率时钟寄存器
reg[2:
0]uart_ctrl;//波特率选择寄存器
always@(posedgeclkorposedgerst_n)
if(rst_n)
cnt<=13'd0;
elseif((cnt==5207)||!
bps_start)//判断计数是否达到1个脉宽
cnt<=13'd0;
else
cnt<=cnt+1'b1;//波特率时钟启动
always@(posedgeclkorposedgerst_n)begin
if(rst_n)
clk_bps_r<=1'b0;
elseif(cnt==2603)//当波特率计数到一半时,进行采样存储
clk_bps_r<=1'b1;
else
clk_bps_r<=1'b0;
end
assignclk_bps=clk_bps_r;//将采样数据输出给uart_rx模块
endmodule
蓝牙数据接收以及编码代码
moduleuart_rx(
clk,
rst_n,
bps_start,
clk_bps,
rs232_rx,
rx_data,
rx_int,
led,
led_new
);
inputclk;//时钟
inputrst_n;//复位
inputrs232_rx;//接收数据信号
inputclk_bps;//高电平时为接收信号中间采样点
outputbps_start;//接收信号时,波特率时钟信号置位
output[7:
0]rx_data;//接收数据寄存器
outputrx_int;//接收数据中断信号,接收过程中为高
output[9:
0]led;
outputreg[7:
0]led_new;
reg[9:
0]led;
regrs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3;//接收数据寄存器
wireneg_rs232_rx;//表示数据线接收到下沿
always@(posedgeclkorposedgerst_n)begin
if(rst_n)begin
rs232_rx0<=1'b0;
rs232_rx1<=1'b0;
rs232_rx2<=1'b0;
rs232_rx3<=1'b0;
end
elsebegin
rs232_rx0<=rs232_rx;
rs232_rx1<=rs232_rx0;
rs232_rx2<=rs232_rx1;
rs232_rx3<=rs232_rx2;
end
end
assignneg_rs232_rx=rs232_rx3&rs232_rx2&~rs232_rx1&~rs232_rx0;//串口传输线的下沿标志
regbps_start_r;
reg[3:
0]num;//移位次数
regrx_int;//接收中断信号
always@(posedgeclkorposedgerst_n)
if(rst_n)begin
bps_start_r<=1'bz;
rx_int<=1'b0;
end
elseif(neg_rs232_rx)begin//
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- FPGA 蓝牙 控制 电子琴