PCIe clock distribution in embedded systems.docx

PCIe clock distribution in embedded systems.docx

《PCIe clock distribution in embedded systems.docx》由会员分享，可在线阅读，更多相关《PCIe clock distribution in embedded systems.docx（10页珍藏版）》请在冰豆网上搜索。

PCIeclockdistributioninembeddedsystems

PCIeclockdistributioninembeddedsystems

ByIanDobsonandJimHolbrook,IntegratedDeviceTechnologyInc-February19,2009

ThePCIe（peripheral-component-interconnectexpress）protocolishighlydesirableforcommunicationacrossbackplanesinembeddedandothersystemtypes.However,foranembedded-systemenvironmentinwhichbackplaneconnectorpinsareoftenatapremium,PCIe’spreferredclock-distributionscheme—usingastarconfigurationofpoint-to-pointconnections—islessthanideal.YoucandistributeaPCIe-compatibleclockusingasinglemultidropsignalandstillmeetthetightjitterrequirementsofthePCIeGeneration2specification.

ClockinginPCIe

PCIeBaseSpecifications1.1and2.0definethreeclock-distributionmodelsforthe2.5-and5-Gbpssignalingrates（figure1,figure 2, andfigure3）.Thecommon-clockarchitectureisthecommonmethodforavarietyofreasons.First,mostofthecommerciallyavailablechipssupportingPCIeinterfacesuseonlythisarchitecture.Second,thisarchitectureistheonlyonethatdirectlysupportsspread-spectrumclocking,whichcanbeimportantinreducingEMI（electromagnetic-interference）peakingand,hence,simplifiesthetaskofmeetingelectromagneticemissionslimitsforthesystem（Figure4）.Finally,thisarchitectureisthesimplesttoconceptualizeanddesign.

Themostsignificantdisadvantageofthecommon-clockarchitectureistheneedtodistributethereferenceclocktoeachPCIeendpointinthesystem.Theclock’s100-or125-MHzfrequencyandthePCIeprotocol’stightjitterrequirementsfurthercomplicatethistask.For2.5-Gbpsoperation,thelimitis86-psecp-pphasejitterforasamplesetof106samples.The5-Gbpsoperationallimitis3.1-psec-rmsjitter.However,tooperateat5Gbps,atransceiverfirstnegotiatesat2.5Gbpsandthenmovesuptothehigherrateifbothendscandoso.Thatis,ifthesystemsupportsany5-Gbpslinks,thenthereferenceclockmustmeetbothjitterspecifications.

Theseparate-anddata-clockarchitecturesavoidtheselimitationsbutsubstantiallyincreasethecomplexityoftheclock-systemdesignanddon’tsupportspread-spectrumclockingwithouttheuseofsidebandsignaling.Thegoverningspecificationsforreference-clockjitterarePCIeBaseSpecifications1.1and2.0,andPCIeJitter-ModelingRevision1.0DandPCIeJitterandBER（bit-error-rate）Revision1.0detailthemethodforverifyingjittercompliance.Theelectromechanicalspecificationsprovidemechanical-form-factorinformation,electrical-signaldefinition,andfunctionaldefinitions.Someofthesespecifications,suchasCard-ElectromechanicalSpecifications1.1and2.0,alsoprovidejitterbudgetingamongthereferenceclock,transmittingPLL（phase-lockedloop）,receivingPLL,andmedia.Strictlyspeaking,theCard-ElectromechanicalSpecificationappliesonlytoPC-,serverATX-（advanced-technology-extended）,andATX-basedformfactors.Industrygroupshavepublishedadditionalelectromechanicalspecificationstocoverotherformfactors,suchasMini-Card-ElectromechanicalSpecification1.2formobile-computingplatforms.

Formostembeddedsystems,thesespecificationsprovideguidelinesthatdesignerscanuseinwholeorinparttospecifytheembeddedsystem’sPCIeclock-distributionscheme.Forexample,manyoftheCard-ElectromechanicaldocumentsspecifytheuseoftheHCSL（host-clock-signal-level）protocolfordistributingthereferenceclock.However,manyembeddedsystemsuseLVPECL（low-voltage-positive-emitter-coupled-logic）signalingorM-LVDS（multipoint-low-voltage-differentialsignaling）toachieveagreaterreach,noisemargin,orbothontheirclock-distributionnetwork.

Manyembeddedsystemsdistributealargenumberofhigh-speedsignals,includingclocks,acrosstheirbackplanes.Todealwiththeoften-heavyelectricalloadingonthosebackplanes,thesesignalstendtohavepowerfuldriversand,hence,highedgerates.Thissituationpresentsthedangerofcrosstalkandothersignal-integrityproblems,especiallywhenthebackplanehasalighterloadthantheworst-casedesign.AnotherrelateddesignchallengeisthatPCIespecifiesreferenceclocksof100or125MHz,whicharedifficulttodistributecleanlyoveralong,heavilyloadedbackplane.

InadditiontothePCIespecifications’tightjitterlimitsandneedforalongersignalreach,thenumberofsignalsthatcantransitthebackplaneconnectorsandthebackplaneitselfalsoconstrainembeddedsystems.Definingtheconnectorpinoutsisoneofthemorecriticaltaskswhenspecifyingthesystem.

Common-clock-distributionscheme

Duetotheclockfrequencyandjitterconstraints,mostcommon-clock-architecturedesignsdistributetheirreferenceclocksusingpoint-to-pointdifferential-signalingpairs,oneofwhichgoestoeveryPCIeendpointinthesystem.IfyourdesignhasmultiplePCIeendpointsonasinglecard,youcantakeinareference-clockinputfromthebackplaneandprovideaclock-distributionnetworkonthecardusingzero-delaybuffers.Eventhistaskcanbedifficulttodesign,however,giventhejitterconstraintsof5-GbpsPCIeoperation.

Assumingthatyoucoulddesignsuchon-carddistributionschemes,theystillrequireapoint-to-pointconnectionfromthePCIeroottoeverycardinthesystem.Inembeddedsystems,thisrequirementaddsalotofconnectorpinstotheroot-cardslotsandalotoftraceswithspecialroutingrequirementstothebackplane.Italsomeansthattheslotthattherootcardplugsintohasadifferentpinoutfromthatoftheotherslots.

OneapproachtosolvingtheseproblemsistodividethePCIereferenceclockontherootcardanddistributeitacrossthebackplaneusingamultidropM-LVDSandthentomultiplyittothedesiredfrequencyorfrequenciesonthedestinationcards.Althoughconceptuallysimple,thisapproachistrickytoachievewithinthejitterconstraintsofPCIe（Figure5）.

ThisapproachallowsyoutouseanM-LVDSpairtodriveorreceiveaPCIe-compliantreferenceclock.Inmanyembeddedsystems,thecardsoperateasrootsorendpointsdependingontheapplication,theslotassignment,orboth.AcardthatoperatesinonlyoneofthosemodeswouldbesimplerthantheoneinFigure5.Onecardinthesystemwouldactastheroot,generatingareferenceclockmeetingthePCIeconstraintsfromitsonboardcrystal.ThisclockwoulddriveanyonboardPCIedevicesfromaninternalclock-distributionnetwork.Theclockwouldalsogotoanon-PLLdividercircuitthatwoulddivideitfrom100or125MHztothebackplanefrequencyof25MHz.Itwouldthendrivethedivided-downreferenceclocktotherestofthecardsinthesystem.Alltheothercardsinthesystemwoulddisabletheuseoftheironboardclockgenerators,tristatetheirdriversforthereference-clocktraces,andreceivethereferenceclockfromthebackplane.ThisclockwouldmultiplyusingaPLL-basedzero-delaybuffertotherequiredonboardreference-clockfrequencyandthentraveltotheothercards.Thecircuitrythatreceivesandmultipliesthereferenceclockfromthebackplanewouldusuallyresideontherootcardandcouldgeneratethesecondreference-clockfrequency,ifnecessary.ToachievethelowjitterthatPCIerequires,youcanincorporatejitterattenuatorsfortheclocksynthesizerandthezero-delaybuffer.

OneofthemainchallengesofadesignsuchasthisisthatPLLsfilterhigh-frequencyjitterhigherthantheirloopbandwidthbutaddjitteratmodulationfrequencieslowerthantheirloopbandwidth.PLLsalsoinducetrackingskewbecausetheydonotperfectlytrackphaseandfrequencyvariationsofthereference-clockinput.Forabackplane-PCIeimplementationsuchasthisone,whichinvolvestwoormorecascadedPLLsforfrequencygenerationandtranslation,youmusttakegreatcaretominimizephasejitterandPLL-trackingskew.

PCIe-jittermeasurement

Beforedivingintoananalysisoftheperformanceofthisdesign,youmustunderstandtheprocessbywhichPCIeanalyzesjitterperformance.OneoftheoverarchingconcernsofthePCIeJitterWorkingGroupwastoneitheroverspecifynorunderspecifythereferenceclock.Tothatend,thegroupaccountedforthefilteringeffectofthetransmittingandreceivingPLLsandphaseinterpolatoronthereferenceclockandthepeakingeffectsofthesePLLs.

Althoughthegrouphasyettodetailmanyportions,theprocessnowhasfourhigh-levelsteps.First,determinetheaccumulatedphaseerrorforeachcycle.Forserial-datatransfer,theaccumulatedphaseerrorismoreimportantthancycle-to-cyclejitterorperiodjitter,whichareimportantcharacteristicsofparallelbuses.Second,applytheDFT（discreteFouriertransform）totheaccumulatedphase-errordatatochangefromtime-domaintofrequency-domainanalysis.Then,applythesystem-transferfunctiontotheDFToftheaccumulatedphase-errordataandperformaninverseDFTtotransferthefilteredaccumulatedphase-errordatabackintothetimedomain.

YouperformthefilteringanalysisofthePLLsysteminthecomplexfrequencydomainbysettings=jωinthesystem-transferfunctions.Thisequationworkswellforcontinuoussystems,butmostmodernPLLimplementationsarenotpure-analogsystemsbecausetheyhavedigitalcomponents,suchasthephasedetectorandfeedbackdivider;thus,Z-domaindigitalanalysisismoreaccurate.However,briefstudiesbythePCIeJitterWorkingGroupshowedthatS-domainanalysisimposesminimalerror,sothegroupusedS-domainanalysisformodeling.TheS-domainapproximationdeviatessignificantlyfromrealitywhenthereferencefrequencyislessthan10timesthePLLbandwidth,anddesignersmustkeepthatfactinmindwhenselectingaPLL（Reference1）.

Jitter-measurementtips