EDA技术及应用教程赵全利版 部分习题参考答案.docx
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EDA技术及应用教程赵全利版 部分习题参考答案.docx
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EDA技术及应用教程赵全利版部分习题参考答案
部分习题参考答案
3.6习题3
3.合法标识符:
my_counter、Decoder_1、data__BUS、Sig_N
非法标识符:
2FFT、Sig_#N、Not-Ack、ALL_RST_、return、entity
7.参考程序为:
entityNOR2ais
Port(A,B:
instd_logic;
C:
outstd_logic);
endNOR2a;
15.Q=”00100100”
4.4习题41.用PROCESS语句和CASE-WHEN语句,参考程如下:
libraryieee;
useieee.std_logic_1164.all;
entitydecoder3_8is
port(a,b,c,g1,g2a,g2b:
instd_logic;
y:
outstd_logic_vector(7downto0));
enddecoder3_8;
architectureaofdecoder3_8is
signaldz:
std_logic_vector(2downto0);
begin
dz<=c&b&a;
process(dz,g1,g2a,g2b)
begin
if(g1='1'andg2a='0'andg2b='0')then
casedzis
when"000"=>y<="11111110";
when"001"=>y<="11111101";
when"010"=>y<="11111011";
when"011"=>y<="11110111";
when"100"=>y<="11101111";
when"101"=>y<="11011111";
when"110"=>y<="10111111";
when"111"=>y<="01111111";
whenothers=>y<="XXXXXXXX";
endcase;
else
y<="11111111";
endif;
endprocess;
end;
用WHEN-ELSE语句,参考程序如下:
……
architecturea1ofdecoder3_8is
signaldz:
std_logic_vector(2downto0);
begin
dz<=c&b&a;
dout<="11111110"whendz="000"else
"11111101"whendz="001"else
"11111011"whendz="010"else
"11110111"whendz="011"else
"11101111"whendz="100"else
"11011111"whendz="101"else
"10111111"whendz="110"else
"01111111"whendz="111"else
"XXXXXXXX";
enda1;
2.参考程序如下:
entityv74x148is
port(s:
instd_logic;
i:
instd_logic_vector(7downto0);
y:
outstd_logic_vector(2downto0);
yex,ys:
outstd_logic);
endv74x148;
architecturebehaveofv74x148is
begin
process(s,i)
variablej,k:
integerrange7downto0;
variabledone:
bit;
begin
done:
=‘0’;ys<=’0’;
ifs=‘1’thenyex<=’1’;ys<=‘1’;y<=“111”;
else
forjin7downto0loop
ifdone=‘1’thennull;
elsifi(j)=‘0’then
done:
=’1’;yex<=’0’;ys<=’1’;k<=7-j;
y<=conv_std_logic_vector(k,2downto0);
endif;
endloop;
endif;
endprocess;
endbehave;
3.参考程序如下:
5.参考程序如下:
1)同步置位/复位的D触发器。
libraryieee;
useieee.std_logic_1164.all;
entitysync_rsdffis
port(d,clk:
instd_logic;
set:
instd_logic;
reset:
instd_logic;
q,qb:
outstd_logic);
endsync_rsdff;
architecturertl_arcofsync_rsdffis
process(clk)
begin
if(clk'eventandclk='1')then
if(set='0'andreset='1')then
q<='1';
qb<='0';
elsif(set='1'andreset='0')then
q<='0';
qb<='1';
else
q<=d;
qb<=notd;
endif;
endprocess;
endrtl_arc;
2)异步复位的D触发器
libraryieee;
useieee.std_logic_1164.all;
entitydff2is
port(D,clk,clr:
instd_logic;
Q:
outstd_logic);
endentitydff2;
architectureoneofdff2is
begin
process(clk,D,clr)
begin
ifclr='1'then
Q<='0';
Elsifclk'eventandclk='1'then
Q<=D;
endif;
endprocess;
endarchitectureone;
6.参考程序如下
libraryieee;
useieee.std_logic_1164.all;
entitymuxisport(
d:
instd_logic_vector(3downto0);
s:
instd_logic_vector(2downto0);
y:
outstd_logic);
endmux;
architecturearchmuxofmuxis
begin
mux8_1:
process(s,d)
begin
ifs="000"thenx<=d(0);
elsifs="001"thenx<=d
(1);
elsifs="010"thenx<=d
(2);
elsifs="011"thenx<=d(3);
elsifs="100"thenx<=d(4);
elsifs="101"thenx<=d(5);
elsifs="110"thenx<=d(6);
elsex<=d(7);
endif;
endprocessmux8_1;
endarchmux;
7.参考程序如下:
先设计1位加法器:
libraryIEEE;
useIEEE.std_logic_1164.all;
entityadderis
port(a:
instd_logic;
b:
instd_logic;
cin:
instd_logic;
sum:
outstd_logic;
cout:
outstd_logic);
endadder;
architecturertlofadderis
begin
sum<=(axorb)xorcin;
cout<=(aandb)or(cinanda)or(cinandb);
endrtl;
然后设计8位全加器:
libraryIEEE;
useIEEE.std_logic_1164.all;
entityadder8is
generic(N:
integer:
=8);
port(a:
instd_logic_vector(Ndownto1);
b:
instd_logic_vector(Ndownto1);
cin:
instd_logic;
sum:
outstd_logic_vector(Ndownto1);
cout:
outstd_logic);
endadder8;
architecturestructuralofadderNis
componentadder
port(a:
instd_logic;
b:
instd_logic;
cin:
instd_logic;
sum:
outstd_logic;
cout:
outstd_logic);
endcomponent;
signalcarry:
std_logic_vector(0toN);
begin
carry(0)<=cin;
cout<=carry(N);
gen:
forIin1toNgenerate
add:
adderportmap(
a=>a(I),
b=>b(I),
cin=>carry(I-1),
sum=>sum(I),
cout=>carry(I));
endgenerate;
endstructural;
8.参考程序如下:
10.参考程序如下:
libraryieee;
useieee.std_logic_1164.all;
entityjkis
port(j,k,clk,rst:
instd_logic;
q,nq:
bufferstd_logic);
end;
architecturebehaveofjkis
signalq_s,nq_s:
std_logic;
begin
process(j,k,clk,rst)
begin
if(clk'eventandclk='1')then
ifrst=1then
q_s<='0';
nq_s<='1';
if(j='0')and(k='1')then
q_s<='0';
nq_s<='1';
elsif(j='1')and(k='0')then
q_s<='1';
nq_s<='0';
elsif(j='1')and(k='1')then
q_s<=notq;
nq_s<=notnq;
endif;
endif;
endif;
q<=q_s;
nq<=nq_s;
endprocess;
end;
11.参考程序如下:
(a)libraryieee;
useieee.std_logic_1164.all;
entitymuxisport(
ain,bin:
instd_logic_vector(1downto0);
sel:
instd_logic_vector(1downto0);
count:
outstd_logic_vector(1downto0));
endmux;
architecturearchmux1ofmuxis
begin
mux4_1:
process(ain,bin,sel)
begin
ifsel="00"then
count<=ainorbin;
elsifsel="01"then
count<=ainnandbin;
elsifsel="10"then
count<=ainxorbin;
elsifsel="11"then
count<=notbin;
else
count<="xx";
endif;
endprocessmux4_1;
endarchmux1;
(b)
architecturearchmux2ofmuxis
signaltemp_sel:
integerrangeoto3;
begin
mux4_1:
process(ain,bin,sel)
begin
temp_sel<='0';
if(sel(0)='1')then
temp_sel<=temp_sel+1;
endif;
if(sel
(1)='1')then
temp_sel<=temp_sel+2;
endif;
casetemp_selis
when0=>count<=ainorbin;
when1=>count<=ainnandbin;
when2=>count<=ainxorbin;
when3=>count<=notbin;
whenothers=>count<='xx';
endcase;
endprocessmux4_1;
endarchmux2;
(c)
architecturearchmux3ofmuxis
begin
count<=ainorbinwhensel='00'else
count<=ainnandbinwhensel='01'else
count<=ainxorbinwhensel='01'else
count<=notbinwhensel='01'else
count<='xx';
endarchitecturearchmux3;
12.参考程序如下:
libraryieee;
useieee.std_logic_1164.all;
entitydff_latchis
port
(clk,din:
instd_logic;
qout:
outstd_logic);
enddff_latch;
architecturemaxpldofdff_latchis
signaltemp:
std_logic;
begin
p1:
process(clk,temp)
begin
if(enable='1')then
q<=nottemp;
endif;
endprocessp1;
p2:
process(din,clk)
begin
if(clk'eventandclk='1')then
temp<=din;
endif;
endprocess;
endmaxpld;
13.参考程序如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounter_up_down_24is
port(reset,ctrl,follow,clk:
instd_logic;
cin:
instd_logic_vector(4downto0);
cout:
outstd_logic_vector(4downto0);
jin,jie:
outstd_logic);
endcounter_up_down_24;
architecturertlofcounter_up_down_24is
signaltemp:
std_logic_vector(4downto0);
begin
process(clk,reset,ctrl,follow,cin)
begin
ifreset='0'then
temp<="00000";
jin<='1';
jie<='1';
elsiffollow='0'then
temp<=cin;
elsif(clk'eventandclk='0')then
ifctrl='1'then
if(temp=23)then
temp<="00000";
jin<='0';
else
temp<=temp+1;
jin<='1';
endif;
else
if(temp=0)then
temp<="10111";
jie<='0';
else
temp<=temp-1;
jie<='1';
endif;
endif;
endif;
endprocess;
cout<=temp;
endrtl;
14.参考程序如下:
libraryieee;
useieee.std_logic_1164.all;
entityschkis
port(din,clk,clr :
instd_logic;--串行输入数据位/工作时钟/复位信号
ab:
outstd_logic_vector(3downto0));--检测结果输出
endschk;
architecturebehavofschkis
signalq:
integerrange0to8;
signald:
std_logic_vector(4downto0); --5位待检测预置数
begin
d<="10010" ;--5位待检测预置数
process(clk,clr)
begin
ifclr='1'then q<=0;
elsif clk'eventandclk='1'then --时钟到来时,判断并处理当前输入的位
caseqis
when0=> ifdin=d(4)thenq<=1;elseq<=0;endif;
when1=> ifdin=d(3)thenq<=2;elseq<=0;endif;
when2=> ifdin=d
(2)thenq<=3;elseq<=0;endif;
when3=> ifdin=d
(1)thenq<=4;elseq<=0;endif;
when4=> ifdin=d(0)thenq<=5;elseq<=0;endif;
whenothers=> q<=0;
endcase;
endif;
endprocess;
process(q) --检测结果判断输出
begin
ifq=5then ab<="1010"; --序列数检测正确,输出"a"
else ab<="1011"; --序列数检测错误,输出"b"
endif;
endprocess;
endbehav;
5.9习题5
7.参考程序如下所示:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounter_plusis
port(clk,clr:
instd_logic;
dout:
bufferstd_logic_vector(7downto0));
end;
architectureartofcounter_plusis
begin
process(clk,clr)
begin
ifclr='1'thendout<="00000000";
elsifclk'eventandclk='1'then
if(dout=255)thendout<="00000000";--计数到256时清零
elsedout<=dout+1;
endif;
endif;
endprocess;
endart;
仿真波形如图A5.1所示:
图A5.1
8.参考程序如下所示:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounter4bis
port(clk,clr,s,load:
instd_logic;--s=1加法计数,s=0减法计数
din:
instd_logic_vector(7downto0);
dout:
bufferstd_logic_vector(7downto0));
end;
architectureartofcounter4bis
begin
process(clk,clr,s,load,din)
begin
ifclk'eventandclk='1'then
ifclr='1'thendout<=(others=>'0');--清零
elsifload='1'thendout<=din;
elsifs='1'then
if(dout="11111111")thendout<="00000000";--计数到FF时清零
elsedout<=dout+1;
endif;
elsifs='0'then
if(dout="00000000")thendout<="11111111";--设定容量FF
elsedout<=dout-1;
endif;
endif;
endif;
endprocess;
endart;
仿真波形如图A5.2所示:
图A5.2
9.此题可采用原理图输入法,参考原
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