乒乓球游戏机设计doc.docx

乒乓球游戏机设计doc.docx

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乒乓球游戏机设计doc

《EDA课程论文设计》

乒乓球游戏机设计

学校：

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指导教师：

乒乓球游戏机设计

一、实验目的：

（1）采用VHDL语言编写程序，并利用MAX+plusII对程序进行文本编辑输入、仿真测试并得出仿真波形,了解控制信号的时序。

（2）编写设计报告，要求包括方案选择、程序清单、调试过程、测试结果及心得体会。

二、设计内容：

用VHDL设计一个乒乓球游戏机，用开关来模拟球手及裁判，用LED来模拟乒乓球，采用每局十一球赛制，比分由七段显示器显示。

采用按功能分块,将整个电路分成若干子程序,利用不同的子程序来实现记分、显示、键盘控制。

三、设计原理：

1、设计步骤：

（1）对4MHZ信号进行分频,得到所需的1HZ,及七段显示器所需的频率.存为CLOCKMAKE.VHD（注:

仿真时所加的信号频率比这要高。

）。

（2）设计一个子程序来描述裁判,左击球手,右击球手的动作对LED显示的影响,及失球后给出失球信号.这个程序是通过状态机来完成。

存为ＰLAYANGLED.VHD

（3）利用上一子程序给出的矢球信号，来实现记分。

并用按键来控制清零。

DATACONTROL.VHD

（4）从记分子程序得到分数，译码并动态显示出来。

程序名为DATAGET.VHD及DISPLAY.VHD。

（5）写主程序将上面的子程序组合起来。

程序名为PINGPANGGAME.VHD。

按动开关JUDGE可以变动是由哪边开始发球.球发出后,朝对方移去,如果对方接球过早,将使对方得一分,如果球到最近仍不击球,也将丢分,只有在球移动到最进处时,按动击打开关,球才会改变方向朝对方移去.选手每得一分,分数显示加一,满十一分时,局数加一.

2、设计原理图：

四、实验设备：

软件环境：

MAX+PLUSⅡ CPLD软件开发系统，VHDL硬件描述语言

五、设计程序:

（1）顶层模块：

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYpingpanggameIS

PORT（clk_4mhz:

INSTD_LOGIC;

playr:

INSTD_LOGIC;

playl:

INSTD_LOGIC;

judge:

INSTD_LOGIC;

clr:

INSTD_LOGIC;

led:

OUTSTD_LOGIC_VECTOR（8DOWNTO0）;

tclr:

INSTD_LOGIC;

scan:

OUTSTD_LOGIC_VECTOR（5downto0）;

displaycode:

OUTSTD_LOGIC_VECTOR（6DOWNTO0）

）;

ENDpingpanggame;

ARCHITECTUREplayOFpingpanggameIS

COMPONENTclockmake

PORT（CLK:

INSTD_LOGIC;

CLK_DSP:

OUTSTD_LOGIC;

CLK_1HZ:

OUTSTD_LOGIC

）;

ENDCOMPONENT;

COMPONENTplayandled

PORT（

clk:

INSTD_LOGIC;

playr:

INSTD_LOGIC;

playl:

INSTD_LOGIC;

judge:

INSTD_LOGIC;

led:

OUTSTD_LOGIC_VECTOR（9DOWNTO1）;

playrloss:

OUTSTD_LOGIC;

playlloss:

OUTSTD_LOGIC

）;

ENDCOMPONENT;

COMPONENTdisplay

PORT（bcdin:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

displaycode:

OUTSTD_LOGIC_VECTOR（6DOWNTO0）

）;

ENDCOMPONENT;

COMPONENTdataget

PORT（datain:

INSTD_LOGIC_VECTOR（23DOWNTO0）;

clk_dsp:

INSTD_LOGIC;

scan:

OUTSTD_LOGIC_VECTOR（5DOWNTO0）;

bcdout:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）

）;

ENDCOMPONENT;

COMPONENTdatacontrol

PORT（

clk_1hz:

INSTD_LOGIC;

clr:

INSTD_LOGIC;

tclr:

INSTD_LOGIC;

playrloss:

INSTD_LOGIC;

playlloss:

INSTD_LOGIC;

data:

OUTSTD_LOGIC_VECTOR

）;

ENDCOMPONENT;

SIGNALclk_1hz:

STD_LOGIC;

SIGNALclk_dsp:

STD_LOGIC;

SIGNALbcdin:

STD_LOGIC_VECTOR（3DOWNTO0）;

SIGNALplayrloss:

STD_LOGIC;

SIGNALplaylloss:

STD_LOGIC;

SIGNALdata:

STD_LOGIC_VECTOR（23DOWNTO0）;

SIGNALbcdout:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

U1:

clockmakePORTMAP（CLK=>CLK_4MHZ,CLK_DSP=>CLK_DSP,CLK_1HZ=>CLK_1HZ）;

U5:

playandledPORTMAP（playl=>playl,playr=>playr,judge=>judge,clk=>clk_1hz,

led=>led,playlloss=>playlloss,playrloss=>playrloss）;

U6:

datacontrolPORTMAP（clk_1hz=>CLK_1HZ,clr=>clr,tclr=>tclr,playrloss=>playrloss,

playlloss=>playlloss,data=>data）;

U7:

datagetPORTMAP（datain=>data,clk_dsp=>clk_dsp,scan=>scan,bcdout=>bcdout）;

U8:

displayPORTMAP（bcdin=>bcdout,displaycode=>displaycode）;

ENDplay

（2）子模块一：

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYplayandledIS

PORT（

clk:

INSTD_LOGIC;

playr:

INSTD_LOGIC;

playl:

INSTD_LOGIC;

judge:

INSTD_LOGIC;

led:

OUTSTD_LOGIC_VECTOR（9DOWNTO1）;

playrloss:

OUTSTD_LOGIC;

playlloss:

OUTSTD_LOGIC

）;

ENDENTITY;

--LB987654321RB

ARCHITECTUREbehaveOFplayandledIS

TYPESTATEIS（s9r,s8r,s7r,s6r,s5r,s4r,s3r,s2r,s1r,s9l,s8l,s7l,s6l,s5l,s4l,s3l,s2l,s1l,rloss,lloss,rb,lb,nop）;

SIGNALps:

STATE;

SIGNALns:

STATE;

BEGIN

clock:

PROCESS（clk）

BEGIN

IF（clk'EVENTANDclk='1'）THEN

ps<=ns;

ENDIF;

ENDPROCESSclock;

statemachine:

PROCESS（ps,playr,playl,judge）

BEGIN

IF（ps=lb）THEN

IF（judge='0'）THEN

ns<=rb;

ELSIF（playl='0'）THEN

ns<=s9r;

ELSE

ns<=ps;

ENDIF;

ELSIF（ps=rb）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='0'）THEN

ns<=s1l;

ELSE

ns<=ps;

ENDIF;

ELSIF（ps=s9r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s8r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s8r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s7r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s7r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s6r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s6r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s5r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s5r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s4r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s4r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s3r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s3r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s2r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s2r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=s1r;

ELSE

ns<=rloss;

ENDIF;

ELSIF（ps=s1r）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playr='1'）THEN

ns<=rloss;

ELSE

ns<=s2l;

ENDIF;

ELSIF（ps=s1l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s2l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s2l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s3l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s3l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s4l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s4l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s5l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s5l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s6l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s6l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s7l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s7l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s8l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s8l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=s9l;

ELSE

ns<=lloss;

ENDIF;

ELSIF（ps=s9l）THEN

IF（judge='0'）THEN

ns<=lb;

ELSIF（playl='1'）THEN

ns<=lloss;

ELSE

ns<=s8r;

ENDIF;

ELSIF（ps=rloss）THEN

IF（judge='0'）THEN

ns<=lb;

ELSE

ns<=nop;

ENDIF;

ELSIF（ps=lloss）THEN

IF（judge='0'）THEN

ns<=lb;

ELSE

ns<=nop;

ENDIF;

ELSIF（ps=nop）THEN

IF（judge='0'）THEN

ns<=lb;

ELSE

ns<=ps;

ENDIF;

ENDIF;

ENDPROCESSstatemachine;

translate:

PROCESS（ps）

BEGIN

CASEpsIS

WHENrb=>led<="111111110";playlloss<='0';playrloss<='0';

WHENlb=>led<="011111111";playlloss<='0';playrloss<='0';

WHENs9r=>led<="011111111";playlloss<='0';playrloss<='0';

WHENs8r=>led<="101111111";playlloss<='0';playrloss<='0';

WHENs7r=>led<="110111111";playlloss<='0';playrloss<='0';

WHENs6r=>led<="111011111";playlloss<='0';playrloss<='0';

WHENs5r=>led<="111101111";playlloss<='0';playrloss<='0';

WHENs4r=>led<="111110111";playlloss<='0';playrloss<='0';

WHENs3r=>led<="111111011";playlloss<='0';playrloss<='0';

WHENs2r=>led<="111111101";playlloss<='0';playrloss<='0';

WHENs1r=>led<="111111110";playlloss<='0';playrloss<='0';

WHENs1l=>led<="111111110";playlloss<='0';playrloss<='0';

WHENs2l=>led<="111111101";playlloss<='0';playrloss<='0';

WHENs3l=>led<="111111011";playlloss<='0';playrloss<='0';

WHENs4l=>led<="111110111";playlloss<='0';playrloss<='0';

WHENs5l=>led<="111101111";playlloss<='0';playrloss<='0';

WHENs6l=>led<="111011111";playlloss<='0';playrloss<='0';

WHENs7l=>led<="110111111";playlloss<='0';playrloss<='0';

WHENs8l=>led<="101111111";playlloss<='0';playrloss<='0';

WHENs9l=>led<="011111111";playlloss<='0';playrloss<='0';

WHENlloss=>playlloss<='1';led<="111111111";

WHENrloss=>playrloss<='1';led<="111111111";

WHENnop=>led<="111101111";playlloss<='0';playrloss<='0';

WHENOTHERS=>NULL;

ENDCASE;

ENDPROCESStranslate;

ENDbehave;

子模块二：

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdatacontrolIS

PORT（clk_1hz:

INSTD_LOGIC;

clr:

INSTD_LOGIC;

tclr:

INSTD_LOGIC;

playrloss:

INSTD_LOGIC;

playlloss:

INSTD_LOGIC;

data:

OUTSTD_LOGIC_VECTOR（23DOWNTO0）

）;

ENDdatacontrol;

ARCHITECTUREbehaveOFdatacontrolIS

SIGNALlscore0,rscore0:

STD_LOGIC_VECTOR（3DOWNTO0）;

SIGNALlscore10,rscore10:

STD_LOGIC_VECTOR（3DOWNTO0）;

SIGNALltotal,rtotal:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（clk_1hz,clr,tclr,playrloss,playlloss）

BEGIN

IF（tclr='0'）THEN

rtotal<="0000";

ltotal<="0000";

ELSIF（clr='0'）THEN

rscore0<="0000";

lscore0<="0000";

rscore10<="0000";

lscore10<="0000";

ELSIF（clk_1hz'EVENTANDclk_1hz='1'）THEN

IF（playlloss='1'）THEN

IF（rscore0<9）THEN

rscore0<=rscore0+1;

ELSE

rscore0<="0000";

rscore10<="0001";

ENDIF;

IF（rscore0="0000"ANDrscore10="0001"）THEN

rscore0<="0000";

rscore10<="0000";

rtotal<=rtotal+1;

ENDIF;

ENDIF;

IF（playrloss='1'）THEN

IF（lscore0<9）THEN

lscore0<=lscore0+1;

ELSE

lscore0<="0000";

lscore10<="0001";

ENDIF;

IF（lscore0="0000"ANDlscore10="0001"）THEN

lscore0<="0000";

lscore10<="0000";

ltotal<=ltotal+1;

ENDIF;

ENDIF;

ENDIF;

ENDPROCESS;

data（23DOWNTO20）<=ltotal;

data（19DOWNTO16）<=lscore10;

data（15DOWNTO12）<=lscore0;

data（11DOWNTO8）<=rscore10;

data（7DOWNTO4）<=rscore0;

data（3DOWNTO0）<=rtotal;

ENDbehave;

子模块三：

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdatagetIS

PORT（datain:

INSTD_LOGIC_VECTOR（23DOWNTO0）;

clk_dsp:

INSTD_LOGIC;

scan:

OUTSTD_LOGIC_VECTOR（5DOWNTO0）;

bcdout:

OUTSTD_LOGIC_VECTOR（0TO3）

）;

ENDdataget;

ARCHITECTUREbehaveOFdatagetIS

SIGNALS:

STD_LOGIC_VECTOR（2DOWNTO0）:

="000";

BEGIN

U1:

PROCESS（clk_dsp）

BEGIN

IF（clk_dsp'EVENTANDclk_dsp='1'）THEN

IF（S<=4）THEN

S<=S+1;

ELSE

S<="000";

ENDIF;

ENDIF;

ENDPROCESSU1;

U2:

PROCESS（s,datain）

BEGIN

CASEsIS

WHEN"000"=>bcdout<=datain（3downto0）;

scan<="100000";

when"001"=>bcdout<=datain（7downto4）;

scan<="010000";

when"010"=>bcdout<=datain（11downto8）;

scan<="001000";

when"011"=>bc