数字信号处理控制器毕业论文外文翻译.docx
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数字信号处理控制器毕业论文外文翻译.docx
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数字信号处理控制器毕业论文外文翻译
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TMS320LF2407,TMS320LF2406,TMS320LF2402
TMS320LC2406,TMS320LC2404,MS320LC2402
DSPCONTROLLERS
TheTMS320LF240xandTMS320LC240xdevices,newmembersofthe’24xfamilyofdigitalsignalprocessor(DSP)controllers,arepartoftheC2000platformoffixed-pointDSPs.The’240xdevicesoffertheenhancedTMS320architecturaldesignofthe’C2xxcoreCPUforlow-cost,low-power,high-performanceprocessingcapabilities.Severaladvancedperipherals,optimizedfordigitalmotorandmotioncontrolapplications,havebeenintegratedtoprovideatruesinglechipDSPcontroller.Whilecode-compatiblewiththeexisting’24xDSPcontrollerdevices,the’240xoffersincreasedprocessingperformance(30MIPS)andahigherlevelofperipheralintegration.SeetheTMS320x240xdevicesummarysectionfordevice-specificfeatures.
The’240xfamilyoffersanarrayofmemorysizesanddifferentperipheralstailoredtomeetthespecificprice/performancepointsrequiredbyvariousapplications.Flash-baseddevicesofupto32Kwordsofferareprogrammablesolutionusefulfor:
◆Applicationsrequiringfieldprogrammabilityupgrades.
◆DevelopmentandinitialprototypingofapplicationsthatmigratetoROM-baseddevices.
FlashdevicesandcorrespondingROMdevicesarefullypin-to-pincompatible.Notethatflash-baseddevicescontaina256-wordbootROMtofacilitatein-circuitprogramming.
All’240xdevicesofferatleastoneeventmanagermodulewhichhasbeenoptimizedfordigitalmotorcontrolandpowerconversionapplications.Capabilitiesofthismoduleincludecentered-and/oredge-alignedPWMgeneration,programmabledeadbandtopreventshoot-throughfaults,andsynchronizedanalog-to-digitalconversion.Deviceswithdualeventmanagersenablemultiplemotorand/orconvertercontrolwithasingle‘240xDSPcontroller.
Thehighperformance,10-bitanalog-to-digitalconverter(ADC)hasaminimumconversiontimeof500nsandoffersupto16channelsofanaloginput.TheautosequencingcapabilityoftheADCallowsamaximumof16conversionstotakeplaceinasingleconversionsessionwithoutanyCPUoverhead.
Aserialcommunicationsinterface(SCI)isintegratedonalldevicestoprovideasynchronouscommunicationtootherdevicesinthesystem.Forsystemsrequiringadditionalcommunicationinterfaces;the’2407,’2406,and’2404offera16-bitsynchronousserialperipheralinterface(SPI).The’2407and’2406offeracontrollerareanetwork(CAN)communicationsmodulethatmeets2.0Bspecifications.Tomaximizedeviceflexibility,functionalpinsarealsoconfigurableasgeneralpurposeinputs/outputs(GPIO).
Tostreamlinedevelopmenttime,JTAG-compliantscan-basedemulationhasbeenintegratedintoalldevices.Thisprovidesnon-intrusivereal-timecapabilitiesrequiredtodebugdigitalcontrolsystems.AcompletesuiteofcodegenerationtoolsfromCcompilerstotheindustry-standardCodeComposerdebuggersupportsthisfamily.Numerousthirdpartydevelopersnotonlyofferdevice-leveldevelopmenttools,butalsosystem-leveldesignanddevelopmentsupport.
PERIPHERALS
TheintegratedperipheralsoftheTMS320x240xaredescribedinthefollowingsubsections:
●Twoevent-managermodules(EVA,EVB)
●Enhancedanalog-to-digitalconverter(ADC)module
●Controllerareanetwork(CAN)module
●Serialcommunicationsinterface(SCI)module
●Serialperipheralinterface(SPI)module
●PLL-basedclockmodule
●DigitalI/Oandsharedpinfunctions
●Externalmemoryinterfaces(’LF2407only)
●Watchdog(WD)timermodule
Eventmanagermodules(EVA,EVB)
Theevent-managermodulesincludegeneral-purpose(GP)timers,full-compare/PWMunits,captureunits,andquadrature-encoderpulse(QEP)circuits.EVA’sandEVB’stimers,compareunits,andcaptureunitsfunctionidentically.However,timer/unitnamesdifferforEVAandEVB.Table1showsthemoduleandsignalnamesused.Table1showsthefeaturesandfunctionalityavailablefortheevent-managermodulesandhighlightsEVAnomenclature.
EventmanagersAandBhaveidenticalperipheralregistersetswithEVAstartingat7400handEVBstartingat7500h.TheparagraphsinthissectiondescribethefunctionofGPtimers,compareunits,captureunits,andQEPsusingEVAnomenclature.TheseparagraphsareapplicabletoEVBwithregardtofunction—however,module/signalnameswoulddiffer.
Table1.ModuleandSignalNamesforEVAandEVB
EVENTMANAGERMODULES
EVAMODULE
SIGNAL
EVBMODULE
SIGNAL
GPTimers
Timer1
Timer2
T1PWM/T1CMP
T2PWM/T2CMP
Timer3
Timer4
T3PWM/T3CMP
T4PWM/T4CMP
CompareUnits
Compare1
Compare2
Compare3
PWM1/2
PWM3/4
PWM5/6
Compare4
Compare5
Compare6
PWM7/8
PWM9/10
PWM11/12
CaptureUnits
Capture1
Capture2
Capture3
CAP1
CAP2
CAP3
Capture4
Capture5
Capture6
CAP4
CAP5
CAP6
QEP
QEP1
QEP2
QEP1
QEP2
QEP3
QEP4
QEP3
QEP4
ExternalInputs
Direction
ExternalClock
TDIRA
TCLKINA
Direction
ExternalClock
TDIRB
TCLKINB
General-purpose(GP)timers
TherearetwoGPtimers:
TheGPtimerx(x=1or2forEVA;x=3or4forEVB)includes:
●A16-bittimer,up-/down-counter,TxCNT,forreadsorwrites
●A16-bittimer-compareregister,TxCMPR(double-bufferedwithshadowregister),forreadsorwrites
●A16-bittimer-periodregister,TxPR(double-bufferedwithshadowregister),forreadsorwrites
●A16-bittimer-controlregister,TxCON,forreadsorwrites
●Selectableinternalorexternalinputclocks
●Aprogrammableprescalerforinternalorexternalclockinputs
●Controlandinterruptlogic,forfourmaskableinterrupts:
underflow,overflow,timercompare,andperiodinterrupts
●Aselectabledirectioninputpin(TDIR)(tocountupordownwhendirectionalup-/down-countmodeisselected)
TheGPtimerscanbeoperatedindependentlyorsynchronizedwitheachother.ThecompareregisterassociatedwitheachGPtimercanbeusedforcomparefunctionandPWM-waveformgeneration.TherearethreecontinuousmodesofoperationsforeachGPtimerinup-orup/down-countingoperations.InternalorexternalinputclockswithprogrammableprescalerareusedforeachGPtimer.GPtimersalsoprovidethetimebasefortheotherevent-managersubmodules:
GPtimer1forallthecomparesandPWMcircuits,GPtimer2/1forthecaptureunitsandthequadrature-pulsecountingoperations.Double-bufferingoftheperiodandcompareregistersallowsprogrammablechangeofthetimer(PWM)periodandthecompare/PWMpulsewidthasneeded.
Full-compareunits
Therearethreefull-compareunitsoneacheventmanager.ThesecompareunitsuseGPtimer1asthetimebaseandgeneratesixoutputsforcompareandPWM-waveformgenerationusingprogrammabledeadbandcircuit.Thestateofeachofthesixoutputsisconfiguredindependently.Thecompareregistersofthecompareunitsaredouble-buffered,allowingprogrammablechangeofthecompare/PWMpulsewidthsasneeded.
Programmabledeadbandgenerator
Thedeadbandgeneratorcircuitincludesthree8-bitcountersandan8-bitcompareregister.Desireddeadbandvalues(from0to24µs)canbeprogrammedintothecompareregisterfortheoutputsofthethreecompareunits.Thedeadbandgenerationcanbeenabled/disabledforeachcompareunitoutputindividually.Thedeadband-generatorcircuitproducestwooutputs(withorwithoutdeadbandzone)foreachcompareunitoutputsignal.Theoutputstatesofthedeadbandgeneratorareconfigurableandchangeableasneededbywayofthedouble-bufferedACTRregister.
PWMwaveformgeneration
UptoeightPWMwaveforms(outputs)canbegeneratedsimultaneouslybyeacheventmanager:
threeindependentpairs(sixoutputs)bythethreefull-compareunitswithprogrammabledeadbands,andtwoindependentPWMsbytheGP-timercompares.
PWMcharacteristics
CharacteristicsofthePWMsareasfollows:
●16-bitregisters
●ProgrammabledeadbandforthePWMoutputpairs,from0to24µs
●Minimumdeadbandwidthof50ns
●ChangeofthePWMcarrierfrequencyforPWMfrequencywobblingasneeded
●ChangeofthePWMpulsewidthswithinandaftereachPWMperiodasneeded
●External-maskablepoweranddrive-protectioninterrupts
●Pulse-pattern-generatorcircuit,forprogrammablegenerationofasymmetric,symmetric,andfour-spacevectorPWMwaveforms
●MinimizedCPUoverheadusingauto-reloadofthecompareandperiodregisters
Captureunit
Thecaptureunitprovidesaloggingfunctionfordifferenteventsortransitions.ThevaluesoftheGPtimer2counterarecapturedandstoredinthetwo-level-deepFIFOstackswhenselectedtransitionsaredetectedoncaptureinputpins,CAPx(x=1,2,or3forEVA;andx=4,5,or6forEVB).Thecaptureunitconsistsofthreecapturecircuits.
Captureunitsincludethefollowingfeatures:
●One16-bitcapturecontrolregister,CAPCON(R/W)
●One16-bitcaptureFIFOstatusregister,CAPFIFO(eightMSBsareread-only,eightLSBsarewrite-only)
●SelectionofGPtimer2asthetimebase
●Three16-bit2-level-deepFIFOstacks,oneforeachcaptureunit
●ThreeSchmitt-triggeredcaptureinputpins(CAP1,CAP2,andCAP3)—oneinputpinpercaptureunit.[Allinputsaresynchronizedwiththedevice(CPU)clock.Inorderforatransitiontobecaptured,theinputmustholdatitscurrentleveltomeettworisingedgesofthedeviceclock.TheinputpinsCAP1andCAP2canalsobeusedasQEPinputstotheQEPcircuit.]
●User-specifiedtransition(risingedge,fallingedge,orbothedges)detection
●Threemaskableinterruptflags,oneforeachcaptureunit
Enhancedanalog-to-digitalconverter(ADC)module
AsimplifiedfunctionalblockdiagramoftheADCmoduleisshowninFigure1.TheADCmoduleconsistsofa10-bitADCwithabuilt-insample-and-hold(S/H)circuit.FunctionsoftheADCmoduleinclude:
●10-bitADCcorewithbuilt-inS/H
●Fastconversio
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