自动洗衣机控制器ddpp课程设计模板.docx
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自动洗衣机控制器ddpp课程设计模板.docx
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自动洗衣机控制器ddpp课程设计模板
自动洗衣机控制器ddpp课程设计
电子科技大学
数字设计原理与实践
课
程
设
计
报
告
题目:
自动洗衣机控制器
姓名:
魏玉峰
学号:
1、任务与要求
设计内容:
1)进行需求分析,确定总体框架;
2)画出逻辑电路图;
3)对设计电路进行仿真;
设计要求:
假设自动洗衣机的定时操作顺序是,洗衣10min,排水2min,脱水3min,然后停止。
设计出这个自动洗衣机的控制器。
设计提示:
本设计有4个状态,分别为初始状、洗衣系统、排水系统、和脱水状态。
当有复位信号时,系统进入循环控制状态,依次执行操作,可从信号灯观察到所处状态。
2、设计思路的介绍
分析:
洗衣机开机后,自动进入循环状态,分别进行洗衣10min,排水2min,脱水3min的操作,然后回到待机状态。
任意期间输入复位信号都会重新开始进入循环控制状态。
LED指示灯与当前操作对应,处于发光状态。
由以上要求可知,所有状态共4种,分别为初始状态、洗衣状态、排水状态、和脱水状态,即用1个74163计时器,输出的状态与上面一一对应,具体见下表:
0000
待机
0001
洗衣状态
0010
洗衣状态
0011
洗衣状态
0100
洗衣状态
0101
洗衣状态
0110
洗衣状态
0111
洗衣状态
1000
洗衣状态
1001
洗衣状态
1010
洗衣状态
1011
排水状态
1100
排水状态
1101
脱水状态
1110
脱水状态
1111
脱水状态
故可根据上表分别选择输出时的74163对应输出接口。
三、总体方案的选择
经过多次选择与比较最终选择74163,7400来完成电路实现计时功能。
将时钟信号设为1/60hz,即每分钟一个上升沿。
电路中采用16个4输入与非门,1个12输入与非门,1个2输入与非门,1个3输入与非门。
把每一个4输入与非门的四个角分别于74163的Qd、Qc、Qb、Qa相连,而每一个4输入与非门分别对应一个74163的输出状态。
当所输出状态对应了洗衣机状态时,总输出状态将产生变化,从而进行当前操作,具体电路图设计如下:
Clk为时钟信号1/60hz
Input为开关按钮
Clr为复位按钮
Standby代表当前为待机状态
Washing代表当前为洗衣状态
Drainage代表当前为排水状态
Dehydration代表当前为洗衣状态
四、VerilogHDL代码
moduletry3(
clk,
input,
clr,
Standby,
Washing,
Drainage,
Dehydration
);
inputclk;
inputinput;
inputclr;
outputStandby;
outputWashing;
outputDrainage;
outputDehydration;
wireSYNTHESIZED_WIRE_114;
wireSYNTHESIZED_WIRE_115;
wireSYNTHESIZED_WIRE_2;
wireSYNTHESIZED_WIRE_116;
wireSYNTHESIZED_WIRE_117;
wireSYNTHESIZED_WIRE_5;
wireSYNTHESIZED_WIRE_6;
wireSYNTHESIZED_WIRE_7;
wireSYNTHESIZED_WIRE_8;
wireSYNTHESIZED_WIRE_9;
wireSYNTHESIZED_WIRE_10;
wireSYNTHESIZED_WIRE_12;
wireSYNTHESIZED_WIRE_13;
wireSYNTHESIZED_WIRE_16;
wireSYNTHESIZED_WIRE_17;
wireSYNTHESIZED_WIRE_18;
wireSYNTHESIZED_WIRE_23;
wireSYNTHESIZED_WIRE_24;
wireSYNTHESIZED_WIRE_25;
wireSYNTHESIZED_WIRE_34;
wireSYNTHESIZED_WIRE_36;
wireSYNTHESIZED_WIRE_38;
wireSYNTHESIZED_WIRE_39;
wireSYNTHESIZED_WIRE_42;
wireSYNTHESIZED_WIRE_43;
wireSYNTHESIZED_WIRE_44;
wireSYNTHESIZED_WIRE_51;
wireSYNTHESIZED_WIRE_53;
wireSYNTHESIZED_WIRE_78;
wireSYNTHESIZED_WIRE_84;
wireSYNTHESIZED_WIRE_85;
wireSYNTHESIZED_WIRE_86;
wireSYNTHESIZED_WIRE_88;
wireSYNTHESIZED_WIRE_90;
wireSYNTHESIZED_WIRE_91;
wireSYNTHESIZED_WIRE_118;
wireSYNTHESIZED_WIRE_95;
wireSYNTHESIZED_WIRE_96;
wireSYNTHESIZED_WIRE_97;
wireSYNTHESIZED_WIRE_98;
wireSYNTHESIZED_WIRE_99;
wireSYNTHESIZED_WIRE_100;
wireSYNTHESIZED_WIRE_101;
wireSYNTHESIZED_WIRE_102;
wireSYNTHESIZED_WIRE_103;
wireSYNTHESIZED_WIRE_104;
wireSYNTHESIZED_WIRE_105;
wireSYNTHESIZED_WIRE_106;
wireSYNTHESIZED_WIRE_107;
wireSYNTHESIZED_WIRE_108;
wireSYNTHESIZED_WIRE_112;
wireSYNTHESIZED_WIRE_113;
\74163b2v_inst(
.ENT(input),
.CLRN(clr),
.CLK(clk),
.ENP(input),
.LDN(input),
.QA(SYNTHESIZED_WIRE_115),
.QB(SYNTHESIZED_WIRE_116),
.QC(SYNTHESIZED_WIRE_117),
.QD(SYNTHESIZED_WIRE_114)
);
assignSYNTHESIZED_WIRE_105=~(SYNTHESIZED_WIRE_114&SYNTHESIZED_WIRE_115&SYNTHESIZED_WIRE_2&SYNTHESIZED_WIRE_116);
assignSYNTHESIZED_WIRE_2=~SYNTHESIZED_WIRE_117;
assignSYNTHESIZED_WIRE_113=~(SYNTHESIZED_WIRE_5&SYNTHESIZED_WIRE_6&SYNTHESIZED_WIRE_7&SYNTHESIZED_WIRE_8);
assignSYNTHESIZED_WIRE_100=~(SYNTHESIZED_WIRE_9&SYNTHESIZED_WIRE_10&SYNTHESIZED_WIRE_117&SYNTHESIZED_WIRE_12);
assignSYNTHESIZED_WIRE_102=~(SYNTHESIZED_WIRE_13&SYNTHESIZED_WIRE_115&SYNTHESIZED_WIRE_117&SYNTHESIZED_WIRE_16);
assignSYNTHESIZED_WIRE_101=~(SYNTHESIZED_WIRE_17&SYNTHESIZED_WIRE_18&SYNTHESIZED_WIRE_117&SYNTHESIZED_WIRE_116);
assignSYNTHESIZED_WIRE_118=~(SYNTHESIZED_WIRE_114&SYNTHESIZED_WIRE_115&SYNTHESIZED_WIRE_23&SYNTHESIZED_WIRE_24);
assignSYNTHESIZED_WIRE_103=~(SYNTHESIZED_WIRE_25&SYNTHESIZED_WIRE_115&SYNTHESIZED_WIRE_117&SYNTHESIZED_WIRE_116);
assignSYNTHESIZED_WIRE_108=~(SYNTHESIZED_WIRE_114&SYNTHESIZED_WIRE_115&SYNTHESIZED_WIRE_117&SYNTHESIZED_WIRE_116);
assignSYNTHESIZED_WIRE_104=~(SYNTHESIZED_WIRE_114&SYNTHESIZED_WIRE_34&SYNTHESIZED_WIRE_117&SYNTHESIZED_WIRE_36);
assignSYNTHESIZED_WIRE_96=~(SYNTHESIZED_WIRE_114&SYNTHESIZED_WIRE_38&SYNTHESIZED_WIRE_39&SYNTHESIZED_WIRE_116);
assignSYNTHESIZED_WIRE_95=~(SYNTHESIZED_WIRE_114&SYNTHESIZED_WIRE_42&SYNTHESIZED_WIRE_43&SYNTHESIZED_WIRE_44);
assignSYNTHESIZED_WIRE_5=~SYNTHESIZED_WIRE_114;
assignSYNTHESIZED_WIRE_7=~SYNTHESIZED_WIRE_117;
assignSYNTHESIZED_WIRE_8=~SYNTHESIZED_WIRE_116;
assignSYNTHESIZED_WIRE_6=~SYNTHESIZED_WIRE_115;
assignSYNTHESIZED_WIRE_90=~SYNTHESIZED_WIRE_117;
assignSYNTHESIZED_WIRE_91=~SYNTHESIZED_WIRE_116;
assignSYNTHESIZED_WIRE_97=~(SYNTHESIZED_WIRE_51&SYNTHESIZED_WIRE_115&SYNTHESIZED_WIRE_53&SYNTHESIZED_WIRE_116);
assignSYNTHESIZED_WIRE_88=~SYNTHESIZED_WIRE_114;
assignSYNTHESIZED_WIRE_84=~SYNTHESIZED_WIRE_114;
assignSYNTHESIZED_WIRE_86=~SYNTHESIZED_WIRE_117;
assignSYNTHESIZED_WIRE_85=~SYNTHESIZED_WIRE_115;
assignSYNTHESIZED_WIRE_51
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