lab02.docx

lab02.docx

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lab02

Lab2:

MACFIRFilterVerificationUsingHDLCo-Simulation

TargetingSpartan-3EStarterKit

MACFIRFilterVerificationUsingSimultaneousCo-Simulations

Introduction

Inthislab,youwillexaminehowaVHDLmodel（user-defined）orCOREGenerator™softwareIPfilecanbeincorporatedintoSystemGeneratorbyusingblackboxandco-simulationtokens.YouwillusetheblackboxtoinvoketheXilinxiSIMsimulatortoverifythefunctionalityofthemodelandobservetheoutputinthescopeoftheSimulink™tool.TheblackboxandtokencanbeusedatanylevelofhierarchytosimulateaVHDLcodeoranIP（EDIF）netlist.AfterverifyinginHDLco-simulationmode,youwillcreateahardwareco-simulationblockandperformbothhardwareandsoftwareHDLco-simulation.

Note:

Therearecompletedexamplesinthec:

xup\dsp_flow\labs\solutions\lab2directory.

Objectives

Aftercompletingthislab,youwillbeableto:

∙IncorporateacoreasablackboxintoyourdesignandsimulateyourdesignbyusingHDLco-simulationwiththeXilinxiSIMsimulator

∙BuildaninterfacebetweentheblackboxandSimulinkviatheMATLABconfigurationfile

∙UsetheblackboxinadifferentwaytobringthecoreintotheSimulinktoolviahardwareco-simulationandobservetheimprovementinverificationspeed

∙Createahardwareco-simulationblockandperformhardwareandsoftwareco-simulation

DesignDescription

YouareaDSPdesigneratCyberdyneSystems.Yourcompanyisinvestigatingusingdigitalfiltersinsteadofanalogforitssecuritytagdetectorsinanattempttoimproveperformanceandreducethecostoftheoverallsystem.Thiswillenablethecompanytofurtherpenetratethegrowingsecuritymarketspace.Asingle-channel,single-ratefilterisspecifiedbelow:

∙SamplingFrequency（Fs）=3.0MHz

∙Fstop1=540kHz

∙Fpass1=600kHz

∙Fpass2=900kHz

∙Fstop2=960kHz

∙Attenuationonbothsidesofthepassband=54dB

∙Passbandripple=1

CyberdynehaschosentogowithFPGAsduetotheirflexibility,timetomarket,andperformanceadvantagesoverDSPprocessors.YourHDLdesignexperienceislimited.Therefore,SystemGeneratorforDSPappearstobeanexcellentsolutionforimplementingthefilterinanFPGAbecauseyouarealreadyfamiliarwithMathWorksproducts.

Yourdemandingmanagerhasaskedyoutoinvestigateothertechniquesforcreatingasmallerfilterbecausethecompletedesignutilization（includingotherfunctionsinthechip）oftheprototypeistoobig.A50-percentslicereductionshouldenablethecompletedesignintofitintoasmallSpartan™-3orSpartan-3Edevice.Thiswouldprovidetheproductwithasignificantpricereductionandgiveitthecompetitiveedgerequiredtodominatethemarket.Also,itwouldbebeneficialifyoucouldexploittheembeddedmultipliersbecausetherestofthesystemwillnotbeusingthese,andyourmanagerdoesnotwanttowasteresources.

Thecoefficients,thesameasthosegeneratedinLab4,wereconvertedintointegervaluesandstoredinacoefficientfilecalledcoef.coeinthelab3directory.ThiswasrequiredbecausethecoefficientsthataretobeloadedbytheCOREGenerator™softwaresystemmustbeinintegerformat.

Thisfilterissimulatedbyusingastepinputandtheoutputisobserved.Toanalyzetheoutputofthefilter,inputandoutputsignalsaredisplayedinascope.

Procedure

Thislabcomprisesfourprimarysteps.YouwillusetheCOREGeneratorsoftwaresystemtogenerateaMACFIRcore,usingthecoefficientsprovidedinthecoef.coefile,providedinStep1.YouwillalsocreateawrapperfilesothatthecorecanbeinterfacedtotheSimulinkenvironment.InStep2,youwillcompletethedesign.InStep3,youwillperformtheHDLco-simulationverification.Step4guidesyouthroughsimulatingthedesignthroughhardwareco-simulation.

Foreachprocedurewithinaprimarystep,therearegeneralinstructions（indicatedbythe

symbol）.Thesegeneralinstructionsonlyprovideabroadoutlineforperformingtheprocedure.Belowthesegeneralinstructions,youwillfindaccompanyingstep-by-stepdirectionsandillustratedfiguresthatprovidemoredetailforperformingtheprocedure.Ifyoufeelconfidentaboutcompletingaprocedure,youcanskipthestep-by-stepdirectionsandmoveontothenextgeneralinstruction.

GeneratingaMACFIRCoreStep1

GeneralFlowforthisLab:

Step4:

VerifyingthroughHardware

Step3:

PerformingHDLCo-Simulation

Step2:

CompletingtheMACFIRDesign

Step1:

GeneratingaMACFIRCore

UsetheCOREGeneratorsoftwaresystemtogenerateasingle-channel,single-rateMACFIRcoretargetingtheSpartan™-3Efamily.

❶SelectStartProgramsXilinxISE8.2iAccessoriesCoreGenerator

❷ClickCreateaNewProjectintheGettingStarteddialogbox

❸Browsetothec:

\xup\dsp_flow\labs\lab2directoryandclickOK

Figure2-1.DirectorySelectionWindow

❹ClickYesinthedialogboxwhichindicatesthatthecoregendirectorydoesnotexistandasksifitisokaytocreatethedirectory

❺

SelectthefollowingoptionsintheParttabandclickOK

Figure2-2.PartSelectionWindow

❻SelecttheMACFIRFilter5.1coreafterdouble-clickingDigitalSignalProcessingFiltersintheleftwindow

Figure2-3.PartSelectionWindow

❼Double-clicktheMACFIR5.1Coreentrytoopentheconfigurationdialogbox

❽SelectthefollowingoptionsinthefivestepsoftheMACFIRconfigurationdialogboxes

Page1

¡ComponentName:

fir

¡SingleRateFIR:

Selected

¡Channels:

1

Page2

¡Taps:

92

¡ImpulseResponse:

Symmetric

¡CoefficientWidth:

12

¡NumberofCoefficientSets:

1

¡CoefficientType:

Signed

¡CoefficientBufferType:

BlockMemory

Page3

¡DataWidth:

8

¡DataType:

Signed

¡DataBufferType:

BlockRAM

¡ClickLoadCoefficientsandselectthecoef.coefilefromlab2directory

Page4

¡PerformanceOptimization:

Auto

¡SystemClockRate:

276MHz

¡InputSampleRate:

3MHz

¡RegisteredOutput:

Checked

Page5

Showstheconfigurationstatistics.NotetheResultwidth（=27）andLatency（=57）

❾ClickGeneratetogeneratethecoreandclickOKwhensuccessfullygenerated

Notethatthegeneratedlistoffileswhichareofinterest:

fir.mif,COEF_BUFFER.mif,fir.edn,fir.vhd,andfir.vho.

❿ClosetheCOREGenerator™softwaresystem

Openandmodifythewrapperfilefir_blackbox.vhdtoincludeallinput,exceptclockandclock-enable,oftypestd_logic_vector.Typically,thisfilemustbecreatedbytheuser.Thisfileisrequiredtoprovideaclockenabletoaclockedcircuit,whichisessentialfortheinterfacewiththeSystemGeneratorblockset.

❶Openthefir_blackbox.vhdwrapperfilefromthec:

\xup\dsp_flow\labs\lab2directorybyusingeithertheM-EditorortheWordPadapplication

Note:

Thisfileisprovidedtoyouforyourconvenience.Inpractice,thisfilemustbecreatedforacorethatisclockedbutdoesnothaveaclockenable（asinthiscase）.

❷Changetheresetportentryinthefir_blackboxentitytomakeitastd_logic_vectorofsize1.Itshouldlooklikethefollowing:

reset:

instd_logic_vector（0downto0）;

❸UncommenttheU1instance（allsevenlines）toincludetheinstanceofthefircoreblock

❹Saveandclosethefile

CompletingtheMACFIRDesignforHDLCo-SimulationStep2

GeneralFlowforthisLab:

Step4:

VerifyingthroughHardware

Step3:

PerformingHDLCo-Simulation

Step2:

CompletingtheMACFIRDesign

Step1:

GeneratingaMACFIRCore

UsetheMATLABconsolewindowtoopenthefir_bb_hdlcosim.mdlmodelfromthec:

\xup\dsp_flow\labs\lab2directory.AddaBlackBoxblockfromXilinxBlocksetBasicElementstothedesign.Assignthefir_blackbox.vhdfiletotheBlackBoxblock.

❶InMATLAB,typecdc:

\xup\dsp_flow\labs\lab2inthecommandwindow

❸Openthefir_bb_hdlcosim.mdlmodelfromtheMATLABconsolewindow

Amodelwithinput,output,scope,andtheSystemGeneratortokenwillbeopened,asshowninFigure2-4.

Figure2-4.fir_bb_hdlcosimModel

❹AddtheBlackBoxblockfromtheXilinxBlocksetBasicElementslibrarytothedesign

ABlackBoxconfigurationfiledialogboxopens,showingtheavailableVHDLfiles（Figure2-5）.

Figure2-5.BlackBoxConfigurationFileDialogBox

❺Selectthec:

\xup\dsp_flow\labs\lab2\fir_blackbox.vhdfileandclickOpentoassignitasthetop-levelentity

TheBlackBoxtokenwiththeappropriatenumberofportsandportnameswillbeaddedtothedesign,asshowninFigure2-6.

Figure2-6.BlackBoxBlockAddedtotheDesign

Aconfigurationfileisalsoopenedwithatop-levelVHDLentityentrythroughwhichtheBlackBoxwillbeconnectedtothesimulator.Browsethroughtheconfigurationfileandunderstandthemajorcomponentsinthefile.NoticethattheonlyreferencetotheVHDLfileistothetop-levelentity.FortheModelSimsimulatortocompile,itrequirestheentriesofallhierarchicalfilesinappropriateorder.

Figure2-7.PortionoftheAutomaticallyGeneratedConfigurationFileDuringBlackBoxAssociation

❻Addthefollowingentriesbeforethethis_block.addFile（'fir_blackbox.vhd'）;line[line63]

this_block.addFile（'coregen\fir.edn'）;

this_block.addFile（'coregen\COEF_BUFFER.mif'）;

this_block.addFile（'coregen\fir.mif'）;

this_block.addFile（'coregen\fir.vhd'）;

❼Changethelinethatindicatesanoutputportofsize27andoftypeUFIXtoFIXtype,asshownbelow,[line26]

dout_port.setType（'Fix_27_0'）;

❽SelectFileSaveandclosetheeditor

ConnecttheBlackBoxtokentotheinputandoutputofthedesign.SelecttheiSIMSimulatorandperformanHDLco-simulation.

❶ConnecttheBlackBoxtokentobothinputsandtheoutput

Theconnecteddesignshouldlooklikethefigurebelow.

Figure2-8.CompleteDesignIncludingModelSimToken

❸Double-clicktheBlack