密码锁的verilog代码.docx
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密码锁的verilog代码.docx
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modulescan_clk(clkout,clk,rst);
inputrst;
inputclk;
wireclk;
outputclkout;
regclkout_r;
parameterperiod=200000;
reg[31:
0]cnt;
always@(posedgeclkornegedgerst)//·ÖƵ50Hz
begin
if(!
rst)
begin
cnt<={31{1'b0}};
clkout_r<=0;
end
elsebegin
cnt<=cnt+1;
if(cnt==(period>>1)-1)
//É趨ÖÜÆÚʱ¼äµÄÒ»°ë
clkout_r<=#11'b1;
elseif(cnt==period-1)//É趨µÄÖÜÆÚʱ¼ä
begin
clkout_r<=#11'b0;
cnt<=#1'b0;
end
end
end
assignclkout=clkout_r;
endmodule
modulekey_scan(clk,keydrv,rst);
inputclk;
inputrst;
wireclk;
output[3:
0]keydrv;
wire[3:
0]keydrv;
parameters1=4'b1110;
parameters2=4'b1101;
parameters3=4'b1011;
parameters4=4'b0111;
reg[3:
0]current_state;
reg[3:
0]next_state;
always@(posedgeclkornegedgerst)
begin
if(!
rst)
current_state<=s1;
elsecurrent_state<=next_state;
end
always@(current_state)
begin
case(current_state)
s1:
next_state<=s2;
s2:
next_state<=s3;
s3:
next_state<=s4;
s4:
next_state<=s1;
default:
next_state<=s1;
endcase
end
assignkeydrv=current_state;
endmodule
`timescale1ms/1ns
modulemms(enter,clk,
KEYO,KEYI,rst,DIG,Y,right,wrong,change,led_c,clr,led_clr);
inputenter;
outputright;
regright;
outputwrong;
regwrong;
inputchange;
outputled_c;
regled_c;
inputclr;
outputled_clr;
regled_clr;
input[3:
0]KEYO;//ÓëÔ-ÀíͼһÖ£¬ÊǼüÅÌÊä³ö¶Ë¿Ú¸øFPGA
inputclk;
inputrst;
output[3:
0]KEYI;//ÓëÔ-ÀíͼһÖ£¬ÊÇFPGAÊä³ö¸ø¼üÅÌ
wirescanclk;
wire[3:
0]keydrv;
reg[3:
0]keyvalue;
reg[7:
0]temp_r;
reg[3:
0]scankey_o;
reg[3:
0]scankey_i;
wiredis;
output[7:
0]Y;
reg[7:
0]Y_r;
assignY=~Y_r;
output[3:
0]DIG;
reg[3:
0]DIG;
assigndis=&KEYO;
regdis_pre;
assignKEYI=keydrv;
scan_clkkey_clk(
.clk(clk),
.clkout(scanclk),
.rst(rst)
);
key_scankey_scan(
.clk(scanclk),
.keydrv(keydrv),
.rst(rst)
);
always@(posedgeclkornegedgerst)begin
if(rst==1'b0)begin
scankey_o<=4'b0;
scankey_i<=4'b0;
dis_pre<=dis;
endelseif(clk==1'b1)begin
dis_pre<=dis;
if((dis==1'b0)&&(dis_pre==1'b1))begin
scankey_o<=keydrv;
scankey_i<=KEYO;
temp_r<={scankey_o,scankey_i};
end
end
end
regclkk;
always@(temp_rorrst)begin
if(rst==1'b0)begin//ÒëÂëÊä³ö
keyvalue=4'b1111;
clkk<=1'b0;
end
else
begin
case(temp_r)
8'b1110_1110:
begin
keyvalue<=4'h7;clkk<=1'b1;
end
8'b1110_1101:
begin
keyvalue<=4'h8;clkk<=1'b1;
end
8'b1110_1011:
begin
keyvalue<=4'h9;clkk<=1'b1;
end
8'b1101_1110:
begin
keyvalue<=4'h4;clkk<=1'b1;
end
8'b1101_1101:
begin
keyvalue<=4'h5;clkk<=1'b1;
end
8'b1101_1011:
begin
keyvalue<=4'h6;clkk<=1'b1;
end
8'b1011_1110:
begin
keyvalue<=4'h1;clkk<=1'b1;
end
8'b1011_1101:
begin
keyvalue<=4'h2;clkk<=1'b1;
end
8'b1011_1011:
begin
keyvalue<=4'h3;clkk<=1'b1;
end
8'b0111_1101:
begin
keyvalue<=4'h0;clkk<=1'b1;
end
default:
begin
keyvalue<=4'b1111;clkk<=1'b0;
end
endcase
end
end
reg[2:
0]cnt;
always@(negedgerstorposedgeclkk)
beginif(!
rst)begincnt<=0;RG<=0;end
else
begincnt<=cnt+1;RG<={keyvalue,RG[15:
4]};end
end
//output[15:
0]RG;
reg[15:
0]RG;
/*
always@(cnt)
if(!
rst)RG<=0;
elsebegin
case(cnt)
3'b001:
beginRG[3:
0]<=keyvalue;end
3'b010:
beginRG[7:
4]<=keyvalue;end
3'b011:
beginRG[11:
8]<=keyvalue;end
3'b100:
beginRG[15:
12]<=keyvalue;end
default:
RG<=RG;
endcase
end
*/
reg[1:
0]js;
always@(posedgescanclk)
begin
if(!
rst)js<=0;
else
js<=js+1;
end
always@(js)
begin
if(!
rst)DIG<=0;
else
begin
case(js)
2'b00:
beginDIG<=4'b0111;A<=RG[3:
0];end
2'b01:
beginDIG<=4'b1011;A<=RG[7:
4];end
2'b10:
beginDIG<=4'b1101;A<=RG[11:
8];end
2'b11:
beginDIG<=4'b1110;A<=RG[15:
12];end
endcase
end
end
reg[3:
0]A;
always@(Aorrst)
begin
if(rst==1'b0)//ÒëÂëÊä³ö
Y_r<=8'b0000_0000;
elsebegin
Y_r=8'b0000_0000;
case(A)
//5'hh:
Y-r=8'b0000_0000;//wuxianshi
4'h0:
Y_r=8'b0011_1111;//0
4'h1:
Y_r=8'b0000_0110;//1
4'h2:
Y_r=8'b0101_1011;//2
4'h3:
Y_r=8'b0100_1111;//3
4'h4:
Y_r=8'b0110_0110;//4
4'h5:
Y_r=8'b0110_1101;//5
4'h6:
Y_r=8'b0111_1101;//6
4'h7:
Y_r=8'b0000_0111;//7
4'h8:
Y_r=8'b0111_1111;//8
4'h9:
Y_r=8'b0110_1111;//9
//4'b0001:
Y_r=8'b1000_0000;//.
default:
Y_r=8'b0100_1001;
endcase
end
end
reg[15:
0]MM;
always@(enter)
begin
if(!
enter)beginright<=1'b0;wrong<=1'b0;
//MM<=16'b0001_0010_0011_0100;
end
else
beginif(enter==1'ba1)
beginif(RG==MM)beginright<=1'b1;wrong<=1'b0;end
elsebeginright<=1'b0;wrong<=1'b1;end
end
end
end
always@(changeorclr)
if(!
clr)
beginled_clr<=1'b0;
begin
if(!
change)led_c<=1'
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