桂林电子科技大学系统实验报告.docx
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桂林电子科技大学系统实验报告.docx
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桂林电子科技大学系统实验报告
表1指令格式,符号和功能
助记符号
指令格式
功能
IN1Rd
1000
××
Rd
将数据存到Rd寄存器
OUT1Rs
1111
Rs
××
(Rs)→LED
CMP1Rd,data
1100
××
Rd
data
(Rd)-data,锁存CY和ZI
CMP2Rs,Rd
1010
Rs
Rd
(Rs)-(Rd),锁存CY和ZI
INCRd
1101
××
Rd
(Rd)+1→Rd
MOV1Rd,data
1001
××
Rd
data
data→Rd
MOV2Rs,Rd
0111
Rs
Rd
Rs→Rd
JMPaddr
1110
××××
addr
addr→PC
JBaddr
1011
××××
addr
若小于,则addr→PC
JLaddr
1000
××××
addr
若小于,则addr→PC
7汇编语言源程序
算法思想为:
采用R0寄存器存输入整数的个数,R1存放输入的整数,R2存放最小负数,用下面的程序实现如下上述功能:
MOV1R0,0功能:
将立即数0→R0(R0用于存放记录输入数的个数)
MOV1R2,FFH将立即数FFH→R2(R2用于存放最小的负数)
L1:
CMP1RO,0A将输入的整数的个数与0A相比较,锁存SF\FS
JLL2小于,则转到L2处执行
JMPL4跳转到L4结束执行
L2:
IN1R1输入一个整数存放于R1当中
INCR0将R0中的数加1
CMP2R1,R2将输入的数与寄存器里的数相比较,锁存SF\FS
JLL3小于,则跳转到L3
JMPL1跳转到L1
L3:
MOV2R1,R2将寄存器R1的数转移到R2当中
JMPL1跳转到L1
L4:
OUT1R2输出最小负数
助记符地址(十六进制)机器代码功能
MOV1R0,000100100000→R0
0100000000
MOV1R2,FFH0210010010FFH→R2
0311111111
L1:
CMP1RO,0A0411000000(R0)-9
0500001010
JLL20600110000L2→PC
0700001010
JMPL40811100000L4→PC
0900010100
L2:
IN1R10A00000001(input)→R1
INCR00B11010000(R0)+1→R0
CMP2R1,R20C10100110(R2)-(R1)
JLL30D10000000L3→PC
0E00010001
JMPL10F11100000L1→PC
1000000100
L3:
MOV2R1,R21101110110(R1)→(R2)
JMPL11211100000L1→PC
1300000100
L4:
OUT1R21411111000(R2)→LED
12软件清单(用VHDL描述)
(1)地址转移逻辑电路(AADR)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYADDRIS
PORT(
I7,I6,I5,I4:
INSTD_LOGIC;
FZ,FC,FS,T4,P1,P2,P3:
INSTD_LOGIC;
SE6,SE5,SE4,SE3,SE2,SE1:
OUTSTD_LOGIC
);
ENDADDR;
ARCHITECTUREAOFADDRIS
BEGIN
SE6<=NOT(NOTFSANDP3ANDT4);
SE5<=NOT((NOTFCANDFZ)ANDP2ANDT4);--FZ=0,跳转
SE4<=NOT(I7ANDP1ANDT4);
SE3<=NOT(I6ANDP1ANDT4);
SE2<=NOT(I5ANDP1ANDT4);
SE1<=NOT(I4ANDP1ANDT4);
ENDA;
(2)算术逻辑运算单元ALU
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYALUIS
PORT(
A:
INSTD_LOGIC_VECTOR(7DOWNTO0);
B:
INSTD_LOGIC_VECTOR(7DOWNTO0);
S1,S0:
INSTD_LOGIC;
BCDOUT:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
CY,ZI,SF:
OUTSTD_LOGIC
);
ENDALU;
ARCHITECTUREAOFALUIS
SIGNALAA,BB,TEMP:
STD_LOGIC_VECTOR(8DOWNTO0);
BEGIN
PROCESS(S1,S0)
BEGIN
IF(S1='0'ANDS0='0')THEN
AA<='0'&A;
BB<='0'&B;
TEMP<=AA+BB;
BCDOUT<=TEMP(7DOWNTO0);
CY<=TEMP(8);
IF(TEMP="100000000"ORTEMP="000000000")THEN
ZI<='1';
ELSE
ZI<='0';
ENDIF;
ELSIF(S1='0'ANDS0='1')THEN
BCDOUT<=A-B;
IF((A(7)='0'ANDB(7)='0')OR(A(7)='1'ANDB(7)='1'))THEN
IF(A
CY<='1';
ZI<='0';
SF<='1';
ELSIF(A=B)THEN
CY<='0';
ZI<='1';
SF<='0';
ELSE
CY<='0';
ZI<='0';
SF<='0';
ENDIF;
ELSIF((A(7)='0')AND(B(7)='1'))THEN
CY<='1';
ZI<='0';
SF<='0';
ELSIF((A(7)='1')AND(B(7)='0'))THEN
CY<='0';
ZI<='0';
SF<='1';
ENDIF;
ELSIF(S1='1'ANDS0='0')THEN
AA<='0'&A;
TEMP<=AA+1;
BCDOUT<=TEMP(7DOWNTO0);
CY<=TEMP(8);
IF(TEMP="100000000")THEN
ZI<='1';
ELSE
ZI<='0';
ENDIF;
ELSE
BCDOUT<="00000000";
CY<='0';
ZI<='0';
ENDIF;
ENDPROCESS;
ENDA;
(3)控制存储器(CONTROM)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCONTROMIS
PORT(
ADDR:
INSTD_LOGIC_VECTOR(5DOWNTO0);
UA:
OUTSTD_LOGIC_VECTOR(5DOWNTO0);
D:
OUTSTD_LOGIC_VECTOR(19DOWNTO0)
);
ENDCONTROM;
ARCHITECTUREAOFCONTROMIS
SIGNALDATAOUT:
STD_LOGIC_VECTOR(25DOWNTO0);
BEGIN
PROCESS(ADDR)
BEGIN
CASEADDRIS
WHEN"000000"=>DATAOUT<="11100110010011110000000010";
WHEN"000010"=>DATAOUT<="10010110010010110100010000";
WHEN"010101"=>DATAOUT<="10000110010110110000000100";
WHEN"000100"=>DATAOUT<="10000010011011110000000101";
WHEN"000101"=>DATAOUT<="10000110110011111000000000";
WHEN"000110"=>DATAOUT<="10001110010010110000000000";
WHEN"010111"=>DATAOUT<="10001100010011110000000000";
WHEN"010000"=>DATAOUT<="10001110010011010000000000";
WHEN"011001"=>DATAOUT<="11100110010011110000000110";
WHEN"011010"=>DATAOUT<="10000100011011110000010100";
WHEN"001011"=>DATAOUT<="11100110010011110010100000";
WHEN"011100"=>DATAOUT<="11100110010011110000010101";
WHEN"011101"=>DATAOUT<="10000010011011110000010010";
WHEN"011110"=>DATAOUT<="11100110010011110000010011";
WHEN"011111"=>DATAOUT<="10000100010001100000000000";
WHEN"010010"=>DATAOUT<="10001111000011110000000000";
WHEN"010011"=>DATAOUT<="01000110010010110000000000";
WHEN"010100"=>DATAOUT<="10000010010111110000000111";
WHEN"000111"=>DATAOUT<="10000110110011111000000000";
WHEN"100000"=>DATAOUT<="01000110010010110000000000";
WHEN"110000"=>DATAOUT<="10000110010011110000000000";
WHEN"011000"=>DATAOUT<="11100110010011110011010001";
WHEN"010001"=>DATAOUT<="01000110010010110000000000";
WHEN"110001"=>DATAOUT<="10000110010011110000000000";
WHENOTHERS=>DATAOUT<="10000110010011110000000000";
ENDCASE;
UA(5DOWNTO0)<=DATAOUT(5DOWNTO0);
D(19DOWNTO0)<=DATAOUT(25DOWNTO6);
ENDPROCESS;
ENDA;
(3)微地址转换器F1
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYF1IS
PORT(
UA5,UA4,UA3,UA2,UA1,UA0:
INSTD_LOGIC;
D:
OUTSTD_LOGIC_VECTOR(5DOWNTO0)
);
ENDF1;
ARCHITECTUREAOFF1IS
BEGIN
D(5)<=UA5;
D(4)<=UA4;
D(3)<=UA3;
D
(2)<=UA2;
D
(1)<=UA1;
D(0)<=UA0;
ENDA;
(4)微地址转换器F2
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYF2IS
PORT(
D:
INSTD_LOGIC_VECTOR(5DOWNTO0);
UA5,UA4,UA3,UA2,UA1,UA0:
OUTSTD_LOGIC
);
ENDF2;
ARCHITECTUREAOFF2IS
BEGIN
UA5<=D(5);
UA4<=D(4);
UA3<=D(3);
UA2<=D
(2);
UA1<=D
(1);
UA0<=D(0);
ENDA;
(5)微地址转换器F3
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYF3IS
PORT(
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
UA7,UA6,UA5,UA4,UA3,UA2,UA1,UA0:
OUTSTD_LOGIC
);
ENDF3;
ARCHITECTUREAOFF3IS
BEGIN
UA7<=D(7);
UA6<=D(6);
UA5<=D(5);
UA4<=D(4);
UA3<=D(3);
UA2<=D
(2);
UA1<=D
(1);
UA0<=D(0);
ENDA;
(6)微地址寄存器(aa)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMMMIS
PORT(
SE:
INSTD_LOGIC;
T2:
INSTD_LOGIC;
D:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
UA:
OUTSTD_LOGIC
);
ENDMMM;
ARCHITECTUREAOFMMMIS
BEGIN
PROCESS(CLR,SE,T2)
BEGIN
IF(CLR='0')THEN
UA<='0';
ELSIF(SE='0')THEN
UA<='1';
ELSIF(T2'EVENTANDT2='1')THEN
UA<=D;
ENDIF;
ENDPROCESS;
ENDA;
(7)时序产生器(COUNTER)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOUNTERIS
PORT(
Q,CLR:
INSTD_LOGIC;
T2,T3,T4:
OUTSTD_LOGIC
);
ENDCOUNTER;
ARCHITECTUREAOFCOUNTERIS
SIGNALX:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
PROCESS(Q,CLR)
BEGIN
IF(CLR='0')THEN
T2<='0';
T3<='0';
T4<='0';
X<="00";
ELSIF(Q'EVENTANDQ='1')THEN
X<=X+1;
T2<=(NOTX
(1))ANDX(0);
T3<=X
(1)AND(NOTX(0));
T4<=X
(1)ANDX(0);
ENDIF;
ENDPROCESS;
ENDA;
(8)1:
2分配器单元(FEN2)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFEN2IS
PORT(
WR,LED_B:
INSTD_LOGIC;
X:
INSTD_LOGIC_VECTOR(7DOWNTO0);
W1,W2:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDFEN2;
ARCHITECTUREAOFFEN2IS
BEGIN
PROCESS(LED_B,WR)
BEGIN
IF(LED_B='0'ANDWR='0')THEN
W2<=X;
ELSE
W1<=X;
ENDIF;
ENDPROCESS;
ENDA;
(9)寄存器单元(LS273)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYLS273IS
PORT(
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
CLK:
INSTD_LOGIC;
O:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDLS273;
ARCHITECTUREAOFLS273IS
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
O<=D;
ENDIF;
ENDPROCESS;
ENDA;
(10)状态条件寄存器单元(LS74)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYLS74IS
PORT(
LDFR:
INSTD_LOGIC;
SF,CY,ZI:
INSTD_LOGIC;
FS,FC,FZ:
OUTSTD_LOGIC
);
ENDLS74;
ARCHITECTUREAOFLS74IS
BEGIN
PROCESS(LDFR)
BEGIN
IF(LDFR'EVENTANDLDFR='1')THEN
FC<=CY;
FZ<=ZI;
FS<=SF;
ENDIF;
ENDPROCESS;
ENDA;
(11)微命令寄存器(MCOMMAND)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYMCOMMANDIS
PORT(
T2,T3,T4,I3,I2,I1,I0:
INSTD_LOGIC;
O:
INSTD_LOGIC_VECTOR(19DOWNTO0);
P3,P1,P2,LOAD,LDPC,LDAR,LDIR,LDR0,LDR1,LDR2,R0_B,R1_B,R2_B,S1,S0,ALU_B,LDAC,LDDR,WR,CS,SW_B,LED_B,LDFR:
OUTSTD_LOGIC
);
ENDMCOMMAND;
ARCHITECTUREAOFMCOMMANDIS
SIGNALDATAOUT:
STD_LOGIC_VECTOR(19DOWNTO0);
BEGINPROCESS(T2)
BEGIN
IF(T2'EVENTANDT2='1')THEN
DATAOUT(19DOWNTO0)<=O(19DOWNTO0);
ENDIF;
P3<=DATAOUT(0)
P2<=DATAOUT
(1);
P1<=DATAOUT
(2);
LDFR<=DATAOUT(3)ANDT4;
LED_B<=DATAOUT(4);
SW_B<=DATAOUT(5);
CS<=DATAOUT(6);
WR<=DATAOUT(7)OR(NOTT3);
LDDR<=DATAOUT(8)ANDT4;
LDAC<=DATAOUT(9)ANDT4;
ALU_B<=DATAOUT(10);
S0<=DATAOUT(11);
S1<=DATAOUT(12);
--DATAOUT(13)对应RS_B信号,DATAOUT(14)对应RD_B信号
R2_B<=(DATAOUT(14)OR(NOTI1)ORI0)AND(DATAOUT(13)OR(NOTI3)ORI2);
R1_B<=(DATAOUT(14)ORI1OR(NOTI0))AND(DATAOUT(13)ORI3OR(NOTI2));
R0_B<=(DATAOUT(14)ORI1ORI0)AND(DATAOUT(13)ORI3ORI2);
LDR2<=T4ANDDATAOUT(15)ANDI1AND(NOTI0);
LDR1<=T4ANDDATAOUT(15)AND(NOTI1)ANDI0;
LDR0<=T4ANDDATAOUT(15)AND(NOTI1)AND(NOTI0);
LDIR<=DATAOUT(16)ANDT3;
LDAR<=DATAOUT(17)ANDT3;
LDPC<=DATAOUT(18)ANDT4;
LOAD<=DATAOUT(19);
ENDPROCESS;
ENDA;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMMMIS
PORT(
SE:
INSTD_LOGIC;
T2:
INSTD_LOGIC;
D:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
UA:
OUTSTD_LOGIC
);
ENDMMM;
ARCHITECTUREAOFMMMIS
BEGIN
PROCESS(CLR,SE,T2)
BEGIN
IF(CLR='0')THEN
UA<='0';
ELSIF(SE='0')THEN
UA<='1';
ELSIF(T2'EVENTANDT2='1')THEN
UA<=D;
ENDIF;
ENDPROCESS;
ENDA;
(12)3选1数据选择器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX3IS
PORT(
ID:
INSTD_LOGIC_VECTOR(7DOWNTO0);
SW_B,CS:
INSTD_LOGIC;
N1,N2:
INSTD_LOGIC_VECTOR(7DOWNTO0);
EW:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDMUX3;
ARCHITECTUREAOFMUX3IS
BEGIN
PROCESS(SW_B,CS)
BEGIN
IF
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