EDA中的VHDL代码.docx
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EDA中的VHDL代码.docx
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EDA中的VHDL代码
Eda中常用的程序集合
1.六十进制计数器:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjsq60is
port(clk:
instd_logic;
co:
outstd_logic;
y:
outintegerrange0to59);
endjsq60;
architectureoneofjsq60is
signalyy:
integerrange0to59;
begin
process(clk)
begin
ifclk'eventandclk='1'then
yy<=yy+1;
endif;
ifyy=15then
co<='1';
else
co<='0';
endif;
endprocess;
y<=yy;
endone;
2.一百进制计数器:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjsq100is
port(clk:
instd_logic;
co:
outstd_logic;
y:
outintegerrange0to99);
endjsq100;
architectureoneofjsq100is
signalyy:
integerrange0to99;
begin
process(clk)
begin
ifclk'eventandclk='1'then
yy<=yy+1;
endif;
ifyy=99then
co<='1';
else
co<='0';
endif;
endprocess;
y<=yy;
endone;
3.三八译码器:
libraryieee;
useieee.std_logic_1164.all;
entityym3_8is
port(a:
instd_logic_vector(2downto0);
b:
outstd_logic_vector(0to7));
endym3_8;
architecturertlofym3_8is
begin
process(a)
begin
caseais
when"000"=>b<="11111110";
when"001"=>b<="11111101";
when"010"=>b<="11111011";
when"011"=>b<="11110111";
when"100"=>b<="11101111";
when"101"=>b<="11011111";
when"110"=>b<="10111111";
when"111"=>b<="01111111";
whenothers=>b<="00000000";
endcase;
endprocess;
endrtl;
4.三人表决器的四种方法:
附程序代码
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybjq3is
port(a,b,c:
instd_logic;
y:
outstd_logic);
end;
architectureoneofbjq3is
begin
y<=(aandb)or(aandc)or(bandc);
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybjq3is
port(a,b,c:
instd_logic;
y:
outstd_logic);
end;
architectureoneofbjq3is
signalm:
std_logic_vector(2downto0);
begin
m<=a&b&c;
y<='0'when(m="000")or(m="001")or(m="010")or(m="100")
else
'1';
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybjq3is
port(a,b,c:
instd_logic;
y:
outstd_logic);
end;
architectureoneofbjq3is
signalm:
std_logic_vector(2downto0);
begin
m<=a&b&c;
withmselect
y<='0'when"000"|"001"|"010"|"100",
'1'whenothers;
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybjq3is
port(m:
instd_logic_vector(2downto0);
y:
outstd_logic);
end;
architectureoneofbjq3is
begin
process(m)
begin
casemis
when"000"|"001"|"010"|"100"=>y<='0';
whenothers=>y<='1';
endcase;
endprocess;
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybjq3is
port(m:
instd_logic_vector(2downto0);
y:
outstd_logic);
end;
architectureoneofbjq3is
begin
process(m)
begin
ifm="000"theny<='0';
elsifm="001"theny<='0';
elsifm="010"theny<='0';
elsifm="011"theny<='1';
elsifm="100"theny<='0';
elsifm="101"theny<='1';
elsifm="110"theny<='1';
elsifm="111"theny<='1';
endif;
endprocess;
end;、
5.八三编码器
libraryieee;
useieee.std_logic_1164.all;
entityyxbm8_3is
port(a:
instd_logic_vector(7downto0);
b:
outstd_logic_vector(2downto0));
endyxbm8_3;
architectureoneofyxbm8_3is
begin
process(a)
begin
ifa(7)<='0'thenb<="000";
elsifa(6)<='0'thenb<="001";
elsifa(5)<='0'thenb<="010";
elsifa(4)<='0'thenb<="011";
elsifa(3)<='0'thenb<="100";
elsifa
(2)<='0'thenb<="101";
elsifa
(1)<='0'thenb<="110";
elseb<="111";
endif;
endprocess;
endone;
6.六选一,四选一数码选择;;;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
entitymux61is
port(d0,d1,d2,d3,d4,d5,a0,a1,a2:
instd_logic;
y:
outstd_logic);
endmux61;
architecturertlofmux61is
signala:
std_logic_vector(2downto0);
begin
process(a0,a1,a2)
begin
a<=a2&a1&a0;
caseais
when"000"=>y<=d0;
when"001"=>y<=d1;
when"010"=>y<=d2;
when"011"=>y<=d3;
when"100"=>y<=d4;
when"101"=>y<=d5;
whenothers=>null;
endcase;
endprocess;
endrtl;
libraryieee;
useieee.std_logic_1164.all;
entitymux41ais
port(d0,d1,d2,d3,a1,a0:
instd_logic;
Y:
outstd_logic);
endentitymux41a;
architectureoneofmux41ais
signalm,n,o,p:
std_logic;
beginm<=(nota1)and(nota0)andd0;
n<=(nota1)anda0andd1;
o<=a1and(nota0)andd2;
p<=a1anda0andd3;
y<=mornoroorp;
endone;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmax4_1IS
PORT(a,b,c,d,s1,s2:
INSTD_LOGIC;
y:
OUTSTD_LOGIC);
ENDENTITYmax4_1;
ARCHITECTUREhf1OFmax4_1IS
SIGNALss:
STD_LOGIC_VECTOR(0TO1);
BEGIN
ss<=s2&s1;
PROCESS(ss)
BEGIN
CASEssIS
WHEN"00"=>y<=a;
WHEN"01"=>y<=b;
WHEN"10"=>y<=c;
WHEN"11"=>y<=d;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREhf1;
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