八位16进制八位10进制频率计设计.docx

八位16进制八位10进制频率计设计.docx

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八位16进制八位10进制频率计设计

EDA综合实习报告一

李爱20111154006电子科学与技术2011级

1.数字频率计的设计

（1）8位16进制频率计

①．主程序：

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYMAINIS

PORT（A,clk1,CLK:

INSTD_LOGIC;

O:

OUTSTD_LOGIC_VECTOR（2DOWNTO0）;

P:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

END;

ARCHITECTUREHEADOFMAINIS

COMPONENTCEPIN

PORT（CLK1:

INSTD_LOGIC;

CNT:

OUTSTD_LOGIC;

RST:

OUTSTD_LOGIC;

LOAD:

OUTSTD_LOGIC）;

ENDCOMPONENT;

COMPONENTJISHU

PORT（CLR:

INSTD_LOGIC;

EN:

INSTD_LOGIC;

FIN:

INSTD_LOGIC;

COUT:

OUTSTD_LOGIC_VECTOR（31DOWNTO0））;

ENDCOMPONENT;

COMPONENTSUOCUN

PORT（LK:

INSTD_LOGIC;

DIN:

INSTD_LOGIC_VECTOR（31DOWNTO0）;

QDOUT:

OUTSTD_LOGIC_VECTOR（31DOWNTO0））;

ENDCOMPONENT;

COMPONENTXIANSHI

PORT（clk:

instd_logic;

Q:

INSTD_LOGIC_VECTOR（31DOWNTO0）;

T:

bufferSTD_LOGIC_VECTOR（2DOWNTO0）;

Y:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDCOMPONENT;

SIGNALNET1,NET2,NET3:

STD_LOGIC;

SIGNALNET4,NET5:

STD_LOGIC_VECTOR（31DOWNTO0）;

BEGIN

U1:

CEPINPORTMAP（CLK1=>CLK,CNT=>NET1,RST=>NET2,LOAD=>NET3）;

U2:

JISHUPORTMAP（CLR=>NET2,EN=>NET1,FIN=>A,COUT=>NET4）;

U3:

SUOCUNPORTMAP（LK=>NET3,DIN=>NET4,QDOUT=>NET5）;

U4:

XIANSHIPORTMAP（clk=>clk1,Q=>NET5,Y=>P,T=>O）;

ENDHEAD;

②．测频

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcepinIS

PORT（CLK1:

INSTD_LOGIC;

CNT:

OUTSTD_LOGIC;

RST:

OUTSTD_LOGIC;

LOAD:

OUTSTD_LOGIC）;

END;

ARCHITECTUREoneOFcepinIS

SIGNALM:

STD_LOGIC;

BEGIN

PROCESS（CLK1）

BEGIN

IFCLK1'EVENTANDCLK1='1'THEN

M<=NOTM;

ENDIF;

ENDPROCESS;

PROCESS（CLK1,M）

BEGIN

IFCLK1='0'ANDM='0'THENRST<='1';

ELSERST<='0';

ENDIF;

ENDPROCESS;

LOAD<=NOTM;

CNT<=M;

ENDone;

③．计数

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYJISHUIS

PORT（CLR:

INSTD_LOGIC;

EN:

INSTD_LOGIC;

FIN:

INSTD_LOGIC;

COUT:

OUTSTD_LOGIC_VECTOR（31DOWNTO0）

）;

END;

ARCHITECTUREtwoOFJISHUIS

SIGNALQ:

STD_LOGIC_VECTOR（31DOWNTO0）;

BEGIN

PROCESS（CLR,EN,FIN）BEGIN

IFCLR='1'THENQ<=（OTHERS=>'0'）;

ELSIFFIN'EVENTANDFIN='1'THEN

IFEN='1'THENQ<=Q+1;

ENDIF;

ENDIF;

ENDPROCESS;

COUT<=Q;

ENDtwo;

④．锁存

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYSUOCUNIS

PORT（LK:

INSTD_LOGIC;

DIN:

INSTD_LOGIC_VECTOR（31DOWNTO0）;

qDOUT:

OUTSTD_LOGIC_VECTOR（31DOWNTO0））;

END;

ARCHITECTUREthreeOFSUOCUNIS

BEGIN

PROCESS（LK,DIN）

BEGIN

IFLK'EVENTANDLK='1'THENqDOUT<=DIN;

ENDIF;

ENDPROCESS;

ENDthree;

⑤显示

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYXIANSHIIS

PORT（clk:

instd_logic;

Q:

INSTD_LOGIC_VECTOR（31DOWNTO0）;

T:

bufferSTD_LOGIC_VECTOR（2DOWNTO0）;

Y:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

END;

ARCHITECTUREfourOFXIANSHIIS

BEGIN

PROCESS（Q,clk,T）

VARIABLEQ1:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

IFclk'eventandclk='1'THEN

Q1:

=Q1+'1';

ENDIF;

ifQ1="0001"then

CASEQ（3downto0）IS

WHEN"0000"=>T<="000";Y<="0111111";

WHEN"0001"=>T<="000";Y<="0000110";

WHEN"0010"=>T<="000";Y<="1011011";

WHEN"0011"=>T<="000";Y<="1001111";

WHEN"0100"=>T<="000";Y<="1100110";

WHEN"0101"=>T<="000";Y<="1101101";

WHEN"0110"=>T<="000";Y<="1111101";

WHEN"0111"=>T<="000";Y<="0000111";

WHEN"1000"=>T<="000";Y<="1111111";

WHEN"1001"=>T<="000";Y<="1101111";

WHEN"1010"=>T<="000";Y<="1110111";

WHEN"1011"=>T<="000";Y<="1111100";

WHEN"1100"=>T<="000";Y<="0111001";

WHEN"1101"=>T<="000";Y<="1011110";

WHEN"1110"=>T<="000";Y<="1111011";

WHEN"1111"=>T<="000";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="0010"then

CASEQ（7downto4）IS

WHEN"0000"=>T<="001";Y<="0111111";

WHEN"0001"=>T<="001";Y<="0000110";

WHEN"0010"=>T<="001";Y<="1011011";

WHEN"0011"=>T<="001";Y<="1001111";

WHEN"0100"=>T<="001";Y<="1100110";

WHEN"0101"=>T<="001";Y<="1101101";

WHEN"0110"=>T<="001";Y<="1111101";

WHEN"0111"=>T<="001";Y<="0000111";

WHEN"1000"=>T<="001";Y<="1111111";

WHEN"1001"=>T<="001";Y<="1101111";

WHEN"1010"=>T<="001";Y<="1110111";

WHEN"1011"=>T<="001";Y<="1111100";

WHEN"1100"=>T<="001";Y<="0111001";

WHEN"1101"=>T<="001";Y<="1011110";

WHEN"1110"=>T<="001";Y<="1111011";

WHEN"1111"=>T<="001";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="0011"then

CASEQ（11downto8）IS

WHEN"0000"=>T<="010";Y<="0111111";

WHEN"0001"=>T<="010";Y<="0000110";

WHEN"0010"=>T<="010";Y<="1011011";

WHEN"0011"=>T<="010";Y<="1001111";

WHEN"0100"=>T<="010";Y<="1100110";

WHEN"0101"=>T<="010";Y<="1101101";

WHEN"0110"=>T<="010";Y<="1111101";

WHEN"0111"=>T<="010";Y<="0000111";

WHEN"1000"=>T<="010";Y<="1111111";

WHEN"1001"=>T<="010";Y<="1101111";

WHEN"1010"=>T<="010";Y<="1110111";

WHEN"1011"=>T<="010";Y<="1111100";

WHEN"1100"=>T<="010";Y<="0111001";

WHEN"1101"=>T<="010";Y<="1011110";

WHEN"1110"=>T<="010";Y<="1111011";

WHEN"1111"=>T<="010";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="0100"then

CASEQ（15downto12）IS

WHEN"0000"=>T<="011";Y<="0111111";

WHEN"0001"=>T<="011";Y<="0000110";

WHEN"0010"=>T<="011";Y<="1011011";

WHEN"0011"=>T<="011";Y<="1001111";

WHEN"0100"=>T<="011";Y<="1100110";

WHEN"0101"=>T<="011";Y<="1101101";

WHEN"0110"=>T<="011";Y<="1111101";

WHEN"0111"=>T<="011";Y<="0000111";

WHEN"1000"=>T<="011";Y<="1111111";

WHEN"1001"=>T<="011";Y<="1101111";

WHEN"1010"=>T<="011";Y<="1110111";

WHEN"1011"=>T<="011";Y<="1111100";

WHEN"1100"=>T<="011";Y<="0111001";

WHEN"1101"=>T<="011";Y<="1011110";

WHEN"1110"=>T<="011";Y<="1111011";

WHEN"1111"=>T<="011";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="0101"then

CASEQ（19downto16）IS

WHEN"0000"=>T<="100";Y<="0111111";

WHEN"0001"=>T<="100";Y<="0000110";

WHEN"0010"=>T<="100";Y<="1011011";

WHEN"0011"=>T<="100";Y<="1001111";

WHEN"0100"=>T<="100";Y<="1100110";

WHEN"0101"=>T<="100";Y<="1101101";

WHEN"0110"=>T<="100";Y<="1111101";

WHEN"0111"=>T<="100";Y<="0000111";

WHEN"1000"=>T<="100";Y<="1111111";

WHEN"1001"=>T<="100";Y<="1101111";

WHEN"1010"=>T<="100";Y<="1110111";

WHEN"1011"=>T<="100";Y<="1111100";

WHEN"1100"=>T<="100";Y<="0111001";

WHEN"1101"=>T<="100";Y<="1011110";

WHEN"1110"=>T<="100";Y<="1111011";

WHEN"1111"=>T<="100";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="0110"then

CASEQ（23downto20）IS

WHEN"0000"=>T<="101";Y<="0111111";

WHEN"0001"=>T<="101";Y<="0000110";

WHEN"0010"=>T<="101";Y<="1011011";

WHEN"0011"=>T<="101";Y<="1001111";

WHEN"0100"=>T<="101";Y<="1100110";

WHEN"0101"=>T<="101";Y<="1101101";

WHEN"0110"=>T<="101";Y<="1111101";

WHEN"0111"=>T<="101";Y<="0000111";

WHEN"1000"=>T<="101";Y<="1111111";

WHEN"1001"=>T<="101";Y<="1101111";

WHEN"1010"=>T<="101";Y<="1110111";

WHEN"1011"=>T<="101";Y<="1111100";

WHEN"1100"=>T<="101";Y<="0111001";

WHEN"1101"=>T<="101";Y<="1011110";

WHEN"1110"=>T<="101";Y<="1111011";

WHEN"1111"=>T<="101";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="0111"then

CASEQ（27downto24）IS

WHEN"0000"=>T<="110";Y<="0111111";

WHEN"0001"=>T<="110";Y<="0000110";

WHEN"0010"=>T<="110";Y<="1011011";

WHEN"0011"=>T<="110";Y<="1001111";

WHEN"0100"=>T<="110";Y<="1100110";

WHEN"0101"=>T<="110";Y<="1101101";

WHEN"0110"=>T<="110";Y<="1111101";

WHEN"0111"=>T<="110";Y<="0000111";

WHEN"1000"=>T<="110";Y<="1111111";

WHEN"1001"=>T<="110";Y<="1101111";

WHEN"1010"=>T<="110";Y<="1110111";

WHEN"1011"=>T<="110";Y<="1111100";

WHEN"1100"=>T<="110";Y<="0111001";

WHEN"1101"=>T<="110";Y<="1011110";

WHEN"1110"=>T<="110";Y<="1111011";

WHEN"1111"=>T<="110";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

elsifQ1="1000"then

CASEQ（31downto28）IS

WHEN"0000"=>T<="111";Y<="0111111";

WHEN"0001"=>T<="111";Y<="0000110";

WHEN"0010"=>T<="111";Y<="1011011";

WHEN"0011"=>T<="111";Y<="1001111";

WHEN"0100"=>T<="111";Y<="1100110";

WHEN"0101"=>T<="111";Y<="1101101";

WHEN"0110"=>T<="111";Y<="1111101";

WHEN"0111"=>T<="111";Y<="0000111";

WHEN"1000"=>T<="111";Y<="1111111";

WHEN"1001"=>T<="111";Y<="1101111";

WHEN"1010"=>T<="111";Y<="1110111";

WHEN"1011"=>T<="111";Y<="1111100";

WHEN"1100"=>T<="111";Y<="0111001";

WHEN"1101"=>T<="111";Y<="1011110";

WHEN"1110"=>T<="111";Y<="1111011";

WHEN"1111"=>T<="111";Y<="1110001";

WHENOTHERS=>NULL;

ENDCASE;endif;ENDPROCESS;

ENDfour;

⑥引脚：

A：

测频端口

CLK：

1Hz输入频率

CLK1：

2048Hz的刷新频率

O：

三八译码器选择端口

P：

数码管显示

（2）8位10进制频率计

①主程序：

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYMAINIS

PORT（CLK1,FSIN:

INSTD_LOGIC;

CLK:

INSTD_LOGIC;E:

OUTSTD_LOGIC_VECTOR（2DOWNTO0）;

DOUT:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

END;

ARCHITECTUREHEADOFMAINIS

COMPONENTJISHU

PORT（CLK,RST,EN:

INSTD_LOGIC;

CQ:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC）;

ENDCOMPONENT;

COMPONENTCEPIN

PORT（CLK:

INSTD_LOGIC;

TSTEN:

OUTSTD_LOGIC;

CLR_CNT:

OUTSTD_LOGIC;

LOAD:

OUTSTD_LOGIC）;

ENDCOMPONENT;

COMPONENTSUOCUN

PORT（LOAD:

INSTD_LOGIC;

DIN:

INSTD_LOGIC_VECTOR（31DOWNTO0）;

DOUT:

OUTSTD_LOGIC_VECTOR（31DOWNTO0））;

ENDCOMPONENT;

COMPONENTXIANSHI

PORT（clk:

instd_logic;

Q:

INSTD_LOGIC_VECTOR（31DOWNTO0）;

T:

bufferSTD_LOGIC_VECTOR（2DOWNTO0）;

Y:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDCOMPONENT;

SIGNALTSTEN:

STD_LOGIC;

SIGNALCLR_CNT:

STD_LOGIC;

SIGNALLOAD:

STD_LOGIC;

SIGNALC1:

STD_LOGIC;

SIGNALC2:

STD_LOGIC;

SIGNALC3:

STD_LOGIC;

SIGNALC4:

ST