EDA课程设计与实现.docx
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EDA课程设计与实现.docx
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EDA课程设计与实现
浦江学院
课程设计报告
(2010—2011学年第一学期)
课程名称:
EDA课程设计与实现_
班级:
浦电子0804
学号:
P1402080419
姓名:
杨昊
指导教师:
朱晓梅
2011年1月
课程设计题目:
闹钟系统设计及实现
目的与任务:
1、巩固专业基础知识及EDA的相关知识;
2、锻炼综合应用所学知识进行小型系统开发设计的能力;
3、培养学生将理论应用于实践的能力;
4、设计一个简单的闹钟系统。
内容和要求:
要求设计一个带闹钟功能的24小时计时器,计时器的外观如图1所示。
图1系统外观
它包括以下几个组成部分:
①显示屏:
4个七段数码管显示当前时间(时:
分)或设置的闹钟时间;一个发光二极管以1HZ的频率跳动,用于显示秒;
②按键key1,用于设置调时还是调分;
③按键key2,用于输入新的时间或新的闹钟时间,每按下一次,时或分加1;
④TIME(时间)键,用于确定新的时间设置;
⑤ALARM(闹钟)键,用于确定新的闹钟时间设置,或显示已设置的闹钟时间;
⑥扬声器,在当前时钟时间与闹钟时间相同时,发出蜂鸣声。
设计内容(原理图以及相关说明、调试过程、结果)
对设计的程序的总体描述,包括框图等
填不满的话可以写写eda的发展史
每个程序都要写上引脚的功能,从哪来到哪去,最好加上
置顶文件
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYALARM_YHIS
PORT(KEY1_YH:
INSTD_LOGIC;
KEY2_YH:
INSTD_LOGIC;
ALARM_BUTTON_YH:
INSTD_LOGIC;
TIME_BUTTON_YH:
INSTD_LOGIC;
CLK_YH:
INSTD_LOGIC;
CLK1_YH:
OUTSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
DISPLAY0_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY1_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY2_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY3_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
SOUND_ALARM1_YH:
OUTSTD_LOGIC);
ENDENTITYALARM_YH;
ARCHITECTUREYHOFALARM_YHIS
COMPONENTKEY1_TRANS_YHIS
PORT(
CLR_YH:
INSTD_LOGIC;
KEY1_YH:
INSTD_LOGIC;
Q_YH:
BUFFERSTD_LOGIC_VECTOR(2DOWNTO0));
ENDCOMPONENT;
COMPONENTKEY2_TRANS_YHIS
PORT(
CLR_YH:
INSTD_LOGIC;
KEY2_YH:
INSTD_LOGIC;
Q2_YH:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
COMPONENTKEYBUFFER_YHIS
PORT(KEY1_CTRL_YH:
INSTD_LOGIC_VECTOR(2DOWNTO0);
KEY2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CLK_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
NEW_TIME0_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME1_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME2_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME3_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
COMPONENTCONTROLLER_YHIS
PORT(
KEY1_YH:
INSTD_LOGIC;
ALARM_BUTTON_YH:
INSTD_LOGIC;
TIME_BUTTON_YH:
INSTD_LOGIC;
CLK_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
LOAD_NEWA_YH:
OUTSTD_LOGIC;
LOAD_NEWC_YH:
OUTSTD_LOGIC;
SHOW_NEW_TIME_YH:
OUTSTD_LOGIC;
SHOWA_YH:
OUTSTD_LOGIC
);
ENDCOMPONENT;
COMPONENTALARMREG_YHIS
PORT(NEW_ALARM_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_ALARM_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_ALARM_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_ALARM_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
LOAD_NEWA_YH:
INSTD_LOGIC;
CLK_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
ALARM_TIME0_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME1_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME2_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME3_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
COMPONENTCOUNTER_YHIS
PORT(NEW_CURRENT_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_CURRENT_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_CURRENT_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_CURRENT_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
LOAD_NEWC_YH:
INSTD_LOGIC;
CLK_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
CURRENT_TIME0_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME1_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME2_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME3_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
COMPONENTDISPLAYDRIVER_YHIS
PORT(ALARM_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
SHOW_NEW_TIME_YH:
INSTD_LOGIC;
SHOWA_YH:
INSTD_LOGIC;
SOUND_ALARM_YH:
OUTSTD_LOGIC;
DISPLAY0_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY1_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY2_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY3_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
COMPONENTFQ_YHIS
PORT(CLK_IN_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
CLK_OUT_YH:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTYUIS
PORT(ASOUNDIN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ASOUNDOUT:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTFQ1_YHIS
PORT(CLK_IN_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
CLK_OUT1_YH:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALS0:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALS1,S60,S61,S62,S63,S70,S71,S72,S73,S80,S81,
S82,S83:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALS2,S3,S4,S5,S9,S10:
STD_LOGIC;
BEGIN
U1:
KEY1_TRANS_YHPORTMAP(CLR_YH,KEY1_YH,S0);
U2:
KEY2_TRANS_YHPORTMAP(CLR_YH,KEY2_YH,S1);
U3:
KEYBUFFER_YHPORTMAP(S0,S1,CLK_YH,CLR_YH,S60,S61,S62,S63);
U4:
CONTROLLER_YHPORT
MAP(KEY1_YH,ALARM_BUTTON_YH,TIME_BUTTON_YH,CLK_YH,
CLR_YH,S9,S2,S3,S4);
U5:
COUNTER_YHPORTMAP(S60,S61,S62,S63,S2,S5,CLR_YH,S80,S81,S82,S83);
U6:
ALARMREG_YHPORTMAP(S60,S61,S62,S63,S9,CLK_YH,CLR_YH,S70,S71,S72,S73);
U7:
DISPLAYDRIVER_YHPORTMAP(S70,S71,S72,S73,S80,S81,S82,S83,
S60,S61,S62,S63,S3,S4,S10,DISPLAY0_YH,
DISPLAY1_YH,DISPLAY2_YH,DISPLAY3_YH);
U8:
YUPORTMAP(S10,CLK_YH,SOUND_ALARM1_YH);
U9:
FQ_YHPORTMAP(CLK_YH,CLR_YH,S5);
U10:
FQ1_YHPORTMAP(CLK_YH,CLR_YH,CLK1_YH);
ENDARCHITECTUREYH;
波形图
分频器
FQ1_YH
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFQ1_YHIS
PORT(CLK_IN_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
CLK_OUT1_YH:
OUTSTD_LOGIC);
ENDENTITYFQ1_YH;
ARCHITECTUREYHOFFQ1_YHIS
BEGIN
CLK1S:
PROCESS(CLK_IN_YH,CLR_YH)IS
SUBTYPET_SHORTISINTEGERRANGE0TO65535;
VARIABLECNT1:
T_SHORT;
BEGIN
IF(CLR_YH='1')THEN
CNT1:
=0;
CLK_OUT1_YH<='0';
ELSIF(RISING_EDGE(CLK_IN_YH))THEN
IF(CNT1<128)THEN
CLK_OUT1_YH<='1';
CNT1:
=CNT1+1;
ELSIF(CNT1<255)THEN
CLK_OUT1_YH<='0';
CNT1:
=CNT1+1;
ELSE
CNT1:
=0;
ENDIF;
ENDIF;
ENDPROCESSCLK1S;
ENDARCHITECTUREYH;
波形图
FQ_YH
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFQ_YHIS
PORT(CLK_IN_YH:
INSTD_LOGIC;
CLR_YH:
INSTD_LOGIC;
CLK_OUT_YH:
OUTSTD_LOGIC);
ENDENTITYFQ_YH;
ARCHITECTUREYHOFFQ_YHIS
BEGIN
CLK1F:
PROCESS(CLK_IN_YH,CLR_YH)IS
SUBTYPET_SHORTISINTEGERRANGE0TO65535;
VARIABLECNT:
T_SHORT;
BEGIN
IF(CLR_YH='1')THEN
CNT:
=0;
CLK_OUT_YH<='0';
ELSIF(RISING_EDGE(CLK_IN_YH))THEN
IF(CNT<7680)THEN
CLK_OUT_YH<='1';
CNT:
=CNT+1;
ELSIF(CNT<15360)THEN
CLK_OUT_YH<='0';
CNT:
=CNT+1;
ELSE
CNT:
=0;
ENDIF;
ENDIF;
ENDPROCESSCLK1F;
ENDARCHITECTUREYH;
原理
波形图
Speak
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYYUIS
PORT(ASOUNDIN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ASOUNDOUT:
OUTSTD_LOGIC);
ENDENTITYYU;
ARCHITECTUREHJCOFYUIS
BEGIN
ASOUNDOUT<=ASOUNDINANDCLK;
ENDARCHITECTURE;
原理
波形图
显示文件
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDISPLAYDRIVER_YHIS
PORT(ALARM_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ALARM_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CURRENT_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME0_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME1_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME2_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
NEW_TIME3_YH:
INSTD_LOGIC_VECTOR(3DOWNTO0);
SHOW_NEW_TIME_YH:
INSTD_LOGIC;
SHOWA_YH:
INSTD_LOGIC;
SOUND_ALARM_YH:
OUTSTD_LOGIC;
DISPLAY0_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY1_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY2_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
DISPLAY3_YH:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDENTITYDISPLAYDRIVER_YH;
ARCHITECTUREYHOFDISPLAYDRIVER_YHIS
SIGNALDISPLAY_TIME_0:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALDISPLAY_TIME_1:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALDISPLAY_TIME_2:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALDISPLAY_TIME_3:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
CTRL:
PROCESS(ALARM_TIME0_YH,ALARM_TIME1_YH,ALARM_TIME2_YH,ALARM_TIME3_YH,
CURRENT_TIME0_YH,CURRENT_TIME1_YH,CURRENT_TIME2_YH,CURRENT_TIME3_YH,
NEW_TIME0_YH,NEW_TIME1_YH,NEW_TIME2_YH,NEW_TIME3_YH,SHOWA_YH,
SHOW_NEW_TIME_YH)IS
BEGIN
IFNOT(ALARM_TIME0_YH=CURRENT_TIME0_YHANDALARM_TIME1_YH=CURRENT_TIME1_YHAND
ALARM_TIME2_YH=CURRENT_TIME2_YHANDALARM_TIME3_YH=CURRENT_TIME3_YH)THEN
SOUND_ALARM_YH<='0';
ELSE
SOUND_ALARM_YH<='1';
ENDIF;
IF(SHOW_NEW_TIME_YH='1')THEN
DISPLAY_TIME_0<=NEW_TIME0_YH;
DISPLAY_TIME_1<=NEW_TIME1_YH;
DISPLAY_TIME_2<=NEW_TIME2_YH;
DISPLAY_TIME_3<=NEW_TIME3_YH;
ELSIF(SHOWA_YH='1')THEN
DISPLAY_TIME_0<=ALARM_TIME0_YH;
DISPLAY_TIME_1<=ALARM_TIME1_YH;
DISPLAY_TIME_2<=ALARM_TIME2_YH;
DISPLAY_TIME_3<=ALARM_TIME3_YH;
ELSIF(SHOWA_YH='0')THEN
DISPLAY_TIME_0<=CURRENT_TIME0_YH;
DISPLAY_TIME_1<=CURRENT_TIME1_YH;
DISPLAY_TIME_2<=CURRENT_TIME2_YH;
DISPLAY_TIME_3<=CURRENT_TIME3_YH;
ELSE
ASSERTFALSEREPORT"UNCERTAINDISPLAY_DRIVERCONTROL!
"
SEVERITYWARNING;
ENDIF;
ENDPROCESSCTRL;
DISP:
PROCESS(DISPLAY_TIME_0,DISPLAY_TIME_1,DISPLAY_TIME_2,
DISPLAY_TIME_3)IS
BEGIN
DISPLAY0_YH<=DISPLAY_TIME_0;
DISPLAY1_YH<=DISPLAY_TIME_1;
DISPLAY2_YH<=DISPLAY_TIME_2;
DISPLAY3_YH<=DISPLAY_TIME_3;
ENDPROCESSDISP;
ENDARCHITECTURE;
原理
波形图
闹铃部分
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL
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