数字电路设计实验报告1.docx
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数字电路设计实验报告1.docx
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数字电路设计实验报告1
数字电路设计实验报告
——洗衣机控制系统
信息工程学院0213301班 杨超 21号
一 . 课题设计任务及技术指标要求
设计任务:
设计制作一个简易全自动洗衣机控制器。
1、洗衣机的功能有洗涤、漂洗和脱水,每个功能持续的时间分别为20秒、15秒和10秒。
2、用一个按键实现洗衣程序的手动选择:
A、单洗涤;B、单漂洗;C、单脱水;D、漂洗和脱水;E、洗涤、漂洗和脱水全过程。
3、在所选择的程序完成之后,控制器应处于停止状态。
4、用一个按键实现暂停洗衣和继续洗衣的控制,暂停后继续洗衣应回到暂停之前保留的状态。
5、用发光二极管指示状态;用数码管以倒计时的方式显示当前状态的剩余时间。
技术指标要求:
能够基本实现真实洗衣机功能要求,提供多种操作选择,使
操作可行性符合当前人们操作习惯,尽可能的在操作和显示方面接近真实的洗
衣机。
二 . 课题设计简述
设计用两个按键来控制整个系统,一个用于选择模式(switch),另一个用于选择开始/停止(pause)。
设置两个信号用于向洗衣机传送着两个消息,识别从暂停状态返回后洗衣机应该进入的状态和模式。
程序分成倒计时模块、按键控制模块、数码管显示模块、发光二极管显示模块、分频模块、防抖动模块以及状态机模块组成。
最后由一个总程序调用。
三 . 设计方案
1、状态框图
2、状态转移图
3、源程序及说明
l 电路主模块wash.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entitywashis -----端口定义
port(clk:
instd_logic;
switch:
instd_logic;
pause:
instd_logic;
lights:
outstd_logic_vector(3downto0);
sell:
outstd_logic_vector(1downto0);
seg:
outstd_logic_vector(6downto0));
endwash;
architecturebehaveofwashis -----子程序调用
componentcount50is
port(clkin:
instd_logic;
clkout:
outstd_logic);
endcomponent;
componentcount25is
port(clkin:
instd_logic;
clkout:
outstd_logic);
endcomponent;
componentstatementis
port(clk:
instd_logic;
switch:
instd_logic;
pause:
instd_logic;
t_xidi:
instd_logic;
t_piaoxi:
instd_logic;
t_tuoshui:
instd_logic;
command:
outstd_logic_vector(2downto0);
present_state:
outstd_logic_vector(2downto0));
endcomponent;
componenttimeis
port(clk_1Hz:
instd_logic;
present_state:
instd_logic_vector(2downto0);
command:
instd_logic_vector(2downto0);
t_xidi:
outstd_logic;
t_piaoxi:
outstd_logic;
t_tuoshui:
outstd_logic;
sec_l,sec_h:
outstd_logic_vector(3downto0));
endcomponent;
componentkeyis
port(clk:
instd_logic;
keyin:
instd_logic;
keyout:
outstd_logic);
endcomponent;
componentdisplayis
port(clk_100Hz:
instd_logic;
sec_l,sec_h:
instd_logic_vector(3downto0);
command:
instd_logic_vector(2downto0);
present_state:
instd_logic_vector(2downto0);
lights:
outstd_logic_vector(3downto0);
sell:
outstd_logic_vector(1downto0);
seg:
outstd_logic_vector(6downto0));
endcomponent;
componentlightwinkis
port(clk_1Hz:
instd_logic;
present_state:
instd_logic_vector(2downto0);
lightsin:
instd_logic_vector(3downto0);
selin:
instd_logic_vector(1downto0);
segin:
instd_logic_vector(6downto0);
lights:
outstd_logic_vector(3downto0);
sell:
outstd_logic_vector(1downto0);
seg:
outstd_logic_vector(6downto0));
endcomponent;
signalclk_10000Hz,clk_100Hz,clk_2Hz,clk_1Hz:
std_logic;
signaltime_xidi,time_piaoxi,time_tuoshui:
std_logic;
signalswitch_n,pause_n:
std_logic;
signalpresent_state:
std_logic_vector(2downto0);
signalcommand:
std_logic_vector(2downto0);
signalsec_low,sec_high:
std_logic_vector(3downto0);
signallights4,lightsout:
std_logic_vector(3downto0);
signalsell2,selout:
std_logic_vector(1downto0);
signalseg7,segout:
std_logic_vector(6downto0);
begin -----端口相应信号替代
link1:
count50portmap(clkin=>clk,clkout=>clk_10000Hz);
link2:
count50portmap(clkin=>clk_10000Hz,clkout=>clk_100Hz);
link3:
count50portmap(clkin=>clk_100Hz,clkout=>clk_1Hz);
link4:
count25portmap(clkin=>clk_100Hz,clkout=>clk_2Hz);
link5:
keyportmap(clk=>clk_100Hz,keyin=>switch,keyout=>switch_n);
link6:
keyportmap(clk=>clk_100Hz,keyin=>pause,keyout=>pause_n);
link7:
statementportmap(clk=>clk_2Hz,switch=>switch_n,pause=>pause_n,t_xidi=>time_xidi,t_piaoxi=>time_piaoxi,t_tuoshui=>time_tuoshui,command=>command,present_state=>present_state);
link8:
timeportmap(clk_1Hz=>clk_1Hz,present_state=>present_state,command=>command,t_xidi=>time_xidi,t_piaoxi=>time_piaoxi,t_tuoshui=>time_tuoshui,sec_l=>sec_low,sec_h=>sec_high);
link9:
displayportmap(clk_100Hz=>clk_100Hz,sec_l=>sec_low,sec_h=>sec_high,command=>command,present_state=>present_state,lights=>lights4,sell=>sell2,seg=>seg7);
link10:
lightwinkportmap(clk_1Hz=>clk_1Hz,present_state=>present_state,lightsin=>lights4,selin=>sell2,segin=>seg7,lights=>lightsout,sell=>selout, seg=>segout);
process
begin
lights<=lightsout;
sell<=selout;
seg<=segout;
endprocess;
end;
l 分频模块count25.vhd和count50.vhd
count50
libraryieee;
useieee.std_logic_1164.all;
entitycount50is
port(clkin:
instd_logic;
clkout:
outstd_logic);
endcount50;
architectureaofcount50is -----端口的定义
signalclk1:
std_logic;
begin
process(clkin)
variablet:
integerrange0to49;
begin
if(clkin'eventandclkin='1')then
if(t=49)then
t:
=0;
clk1<=notclk1; -----当t等于49时输出信号翻转一次实现100分频
elset:
=t+1; -----如果t不等于49则外部时钟变化一次t加1
endif;
endif;
clkout<=clk1;
endprocess;
end;
仿真波形(count50)
count25
libraryieee;
useieee.std_logic_1164.all;
entitycount25is
port(clkin:
instd_logic;
clkout:
outstd_logic);libraryieee;
endcount25;
architectureaofcount25is -----端口的定义
signalclk1:
std_logic;
begin
process(clkin)
variablet:
integerrange0to24;
begin
if(clkin'eventandclkin='1')then
if(t=24)then
t:
=0; -----按照时钟,循环计数
clk1<=notclk1; -----每记25个数,输出信号取反
elset:
=t+1;
endif;
endif;
clkout<=clk1;
endprocess;
end;
仿真波形(count25)
l 防抖电路 key.vhd
libraryieee;
useieee.std_logic_1164.all;
entitykeyis
port(clk:
instd_logic;
keyin:
instd_logic; -----输入的按键信号
keyout:
outstd_logic); -----输出的按键信号
endkey;
architectureaofkeyis
signalcp:
std_logic;
begin
process(clk,keyin)
variablet:
integerrange0to1;
begin
if(clk'eventandclk='1')then
if(keyin='1')then
if(t=1)then
cp<='1'; -----连续两次时钟,输入信号都为1,则输出为1
t:
=0;
else
t:
=t+1; -----计数
endif;
else
cp<='0';
t:
=0;
endif;
endif;
keyout<=cp;
endprocess;
end;
仿真波形(防抖电路)
l 计时模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
useieee.std_logic_arith.all;
entitytimeis
port(clk_1Hz:
instd_logic; -----计时频率
present_state:
instd_logic_vector(2downto0); -----当前状态
command:
instd_logic_vector(2downto0); -----当前命令
t_xidi:
outstd_logic; -----洗涤时钟
t_piaoxi:
outstd_logic; -----漂洗时钟
t_tuoshui:
outstd_logic; -----脱水时钟
sec_l,sec_h:
outstd_logic_vector(3downto0)); -----数码管显示输出的数字
endtime;
architecturebehaveoftimeis
typestate_typeis(stop,switch_mode,xidi,piaoxi,tuoshui);
signalstate:
state_type;
signalxidi_timeup,piaoxi_timeup,tuoshui_timeup:
std_logic;
begin
process(clk_1Hz)
variablec:
integerrange0to1;
variabled:
integerrange0to1;
variablenum1:
integerrange0to15;
variablenum2:
integerrange0to9;
variableinput1:
integerrange0to9;
variableinput2:
integerrange0to9;
variablesec1:
integerrange0to9;
variablesec2:
integerrange0to9;
begin
casecommandis
when"001"=>input1:
=0;input2:
=2; -----洗涤时间20s
when"010"=>input1:
=5;input2:
=1; -----漂洗时间15s
when"011"=>input1:
=0;input2:
=1; -----脱水时间10s
when"100"=>input1:
=5;input2:
=2; -----漂洗和脱水时间25s
when"101"=>input1:
=5;input2:
=4; -----洗涤、漂洗和脱水总时间45s
whenothers=>input1:
=0;input2:
=0;
endcase;
casepresent_stateis -----当前状态输入
when"000"=>state<=stop;
when"001"=>state<=switch_mode;
when"010"=>state<=xidi;
when"011"=>state<=piaoxi;
when"100"=>state<=tuoshui;
whenothers=>state<=stop;
endcase;
if(clk_1Hz'eventandclk_1Hz='1')then
if(state=xidiorstate=piaoxiorstate=tuoshui)then -----处于洗衣状态
if(input1
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