EDA课程设计 5位有符号除法器课设.docx
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EDA课程设计 5位有符号除法器课设.docx
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EDA课程设计5位有符号除法器课设
矩阵键盘输入模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_arith.ALL;
USEIEEE.STD_LOGIC_unsigned.ALL;
ENTITYKEYSCANIS
PORT(clk:
INstd_logic;
rst:
INstd_logic;
lie:
INstd_logic_vector(3DOWNTO0);
fuhao:
INstd_logic;
shuchu:
OUTstd_logic_vector(4DOWNTO0);
hang:
outstd_logic_vector(3DOWNTO0));
ENDKEYSCAN;
ARCHITECTUREarchOFKEYSCANIS
SIGNALdiv_cnt:
std_logic_vector(24downto0);
SIGNALscan_key:
std_logic_vector(3DOWNTO0);
SIGNALkey_code:
std_logic_vector(3DOWNTO0);
SIGNALshuchu_tmp:
std_logic_vector(3DOWNTO0);
BEGIN
hang<=scan_key;
shuchu<=fuhao&shuchu_tmp;
PROCESS(clk,rst)
BEGIN
IF(NOTrst='1')THEN
div_cnt<="0000000000000000000000000";
ELSIF(clk'EVENTANDclk='1')THEN
div_cnt<=div_cnt+1;
ENDIF;
ENDPROCESS;
PROCESS(div_cnt(20downto19))
BEGIN
CASEdiv_cnt(20downto19)IS
WHEN"00"=>scan_key<="1110";
WHEN"01"=>scan_key<="1101";
WHEN"10"=>scan_key<="1011";
WHEN"11"=>scan_key<="0111";
ENDCASE;
ENDPROCESS;
PROCESS(clk,rst)
BEGIN
IF(NOTrst='1')THEN
key_code<="0000";
ELSIF(clk'EVENTANDclk='1')THEN
CASEscan_keyIS
WHEN"1110"=>
CASElieIS
WHEN"1110"=>
key_code<="0000";
WHEN"1101"=>
key_code<="0001";
WHEN"1011"=>
key_code<="0010";
WHEN"0111"=>
key_code<="0011";
WHENOTHERS=>
NULL;
ENDCASE;
WHEN"1101"=>
CASElieIS
WHEN"1110"=>
key_code<="0100";
WHEN"1101"=>
key_code<="0101";
WHEN"1011"=>
key_code<="0110";
WHEN"0111"=>
key_code<="0111";
WHENOTHERS=>
NULL;
ENDCASE;
WHEN"1011"=>
CASElieIS
WHEN"1110"=>
key_code<="1000";
WHEN"1101"=>
key_code<="1001";
WHEN"1011"=>
key_code<="1010";
WHEN"0111"=>
key_code<="1011";
WHENOTHERS=>
NULL;
ENDCASE;
WHEN"0111"=>
CASElieIS
WHEN"1110"=>
key_code<="1100";
WHEN"1101"=>
key_code<="1101";
WHEN"1011"=>
key_code<="1110";
WHEN"0111"=>
key_code<="1111";
WHENOTHERS=>
NULL;
ENDCASE;
WHENOTHERS=>
key_code<="1111";
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS(key_code)
BEGIN
CASEkey_codeIS
WHEN"0000"=>
shuchu_tmp<="0000";
WHEN"0001"=>
shuchu_tmp<="0001";
WHEN"0010"=>
shuchu_tmp<="0010";
WHEN"0011"=>
shuchu_tmp<="0011";
WHEN"0100"=>
shuchu_tmp<="0100";
WHEN"0101"=>
shuchu_tmp<="0101";
WHEN"0110"=>
shuchu_tmp<="0110";
WHEN"0111"=>
shuchu_tmp<="0111";
WHEN"1000"=>
shuchu_tmp<="1000";
WHEN"1001"=>
shuchu_tmp<="1001";
WHEN"1010"=>
shuchu_tmp<="1010";
WHEN"1011"=>
shuchu_tmp<="1011";
WHEN"1100"=>
shuchu_tmp<="1100";
WHEN"1101"=>
shuchu_tmp<="1101";
WHEN"1110"=>
shuchu_tmp<="1110";
WHEN"1111"=>
shuchu_tmp<="1111";
WHENOTHERS=>
NULL;
ENDCASE;
ENDPROCESS;
ENDarch;
输入选择模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYshuru_xzIS
PORT(k0:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(4DOWNTO0);
bcs,cs:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDshuru_xz;
ARCHITECTUREBEHAVEOFshuru_xzIS
BEGIN
PROCESS(k0)
BEGIN
IF(k0='0')THEN
bcs<=DIN;
ELSE
cs<=DIN;
ENDIF;
ENDPROCESS;
ENDBEHAVE;
除法运算模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYchufaIS
PORT(bcs,cs:
instd_logic_vector(4downto0);
shang,yushu:
outstd_logic_vector(4downto0);
cuo:
outstd_logic);
ENDchufa;
ARCHITECTUREcfqofchufais
SIGNALfuhao:
STD_LOGIC_VECTOR(4DOWNTO0);
SIGNALc0,c1,c2,c3:
std_logic_vector(6downto0);
SIGNALb0,b1,b2,b3:
std_logic_vector(6downto0);
BEGIN
PROCESS(cs,bcs)
begin
b3<="000"&bcs(3downto0);c3<=cs(3downto0)&"000";
ifb3>=c3andc3/="0000000"then
shang(3)<='1';b2<=b3-c3;
else
shang(3)<='0';b2<=b3;
endif;
c2<="0"&cs(3downto0)&"00";
ifb2>=c2andc2/="0000000"then
shang
(2)<='1';b1<=b2-c2;
else
shang
(2)<='0';b1<=b2;
endif;
c1<="00"&cs(3downto0)&"0";
ifb1>=c1andc1/="0000000"then
shang
(1)<='1';b0<=b1-c1;
else
shang
(1)<='0';b0<=b1;
endif;
c0<="000"&cs(3downto0);
ifb0>=c0andc0/="0000000"then
shang(0)<='1';yushu(3downto0)<=b0(3downto0)-c0(3downto0);
else
shang(0)<='0';yushu(3downto0)<=b0(3downto0);
endif;
ifcs(3downto0)="0000"then
cuo<='1';else
cuo<='0';
endif;
fuhao<="00000";
fuhao(4)<=bcs(4)XORcs(4);
shang(4)<=fuhao(4);
yushu(4)<=bcs(4);
endprocess;
endcfq;
输出选择模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_arith.ALL;
USEIEEE.STD_LOGIC_unsigned.ALL;
ENTITYshuchu_xzIS
PORT(sw3:
INSTD_LOGIC;
sw4:
INSTD_LOGIC;
ok:
INSTD_LOGIC;
bcs:
INSTD_LOGIC_VECTOR(4DOWNTO0);
cs:
INSTD_LOGIC_VECTOR(4DOWNTO0);
shang:
INSTD_LOGIC_VECTOR(4DOWNTO0);
yushu:
INSTD_LOGIC_VECTOR(4DOWNTO0);
shuchu:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDshuchu_xz;
ARCHITECTURExzOFshuchu_xzIS
BEGIN
PROCESS(bcs,cs,shang,yushu,sw3,sw4)
BEGIN
IF(sw3='0'andsw4='1')THEN
shuchu<=bcs;
ELSIF(sw3='1'andsw4='0')THEN
shuchu<=cs;
ELSIF(sw3='1'andsw4='1')THEN
shuchu<=shang;
ELSE
IF(ok='0')THEN
shuchu<=yushu;
ELSE
shuchu<="00000";
ENDIF;
ENDIF;
ENDPROCESS;
ENDxz;
译码模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_arith.ALL;
USEIEEE.STD_LOGIC_unsigned.ALL;
ENTITYyimaIS
PORT(date:
INSTD_LOGIC_VECTOR(4DOWNTO0);
fuhao:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
shiwei:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
gewei:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDyima;
ARCHITECTUREymOFyimaIS
BEGIN
PROCESS(date)
BEGIN
IF(date(4)='0')THEN
fuhao<="11111111";
ELSEfuhao<="10111111";
ENDIF;
IF(date(3DOWNTO0)>"1001")THEN
shiwei<="11111001";
ELSEshiwei<="11111111";
ENDIF;
CASEdate(3DOWNTO0)IS
WHEN"0000"=>gewei<="11000000";
WHEN"0001"=>gewei<="11111001";
WHEN"0010"=>gewei<="10100100";
WHEN"0011"=>gewei<="10110000";
WHEN"0100"=>gewei<="10011001";
WHEN"0101"=>gewei<="10010010";
WHEN"0110"=>gewei<="10000010";
WHEN"0111"=>gewei<="11011000";
WHEN"1000"=>gewei<="10000000";
WHEN"1001"=>gewei<="10010000";
WHEN"1010"=>gewei<="11000000";
WHEN"1011"=>gewei<="11111001";
WHEN"1100"=>gewei<="10100100";
WHEN"1101"=>gewei<="10110000";
WHEN"1110"=>gewei<="10011001";
WHEN"1111"=>gewei<="10010010";
WHENOTHERS=>gewei<="11111111";
ENDCASE;
ENDPROCESS;
ENDym;
数码管显示模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_unsigned.ALL;
ENTITYshumaguan_xsIS
PORT(clk:
INSTD_LOGIC;
fuhao:
INSTD_LOGIC_VECTOR(7DOWNTO0);
shiwei:
INSTD_LOGIC_VECTOR(7DOWNTO0);
gewei:
INSTD_LOGIC_VECTOR(7DOWNTO0);
shuchu:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
sw:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
END;
ARCHITECTUREaOFshumaguan_xsIS
SIGNALa:
STD_LOGIC_VECTOR(1DOWNTO0):
="00";
BEGIN
pro1:
PROCESS(clk)
BEGIN
IFclk'EVENTANDclk='1'THENa<=a+1;
ENDIF;
ENDPROCESSpro1;
pro2:
PROCESS(a,fuhao,shiwei,gewei)
BEGIN
CASEaIS
WHEN"00"=>shuchu<=gewei;
WHEN"01"=>shuchu<=shiwei;
WHEN"10"=>shuchu<=fuhao;
WHEN"11"=>shuchu<="11111111";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSpro2;
pro3:
PROCESS(a,fuhao,shiwei,gewei)
BEGIN
CASEaIS
WHEN"00"=>sw<="0001";
WHEN"01"=>sw<="0010";
WHEN"10"=>sw<="0100";
WHEN"11"=>sw<="1000";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSpro3;
ENDa;
整体结构图:
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- EDA课程设计 5位有符号除法器课设 EDA 课程设计 符号 法器
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