闹钟代码.docx
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闹钟代码.docx
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闹钟代码
--译码器可将KEYPAD信号转换为0~9的整型数,以直观地表示和处理用户输入的数字。
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydecoderis
Port(keypad:
inSTD_LOGIC_VECTOR(9downto0);
value:
outSTD_LOGIC_VECTOR(3downto0));
enddecoder;
architectureBehavioralofdecoderis
begin
WITHkeypadSELECT
value<="0000"WHEN"0000000001",
"0001"WHEN"0000000010",
"0010"WHEN"0000000100",
"0011"WHEN"0000001000",
"0100"WHEN"0000010000",
"0101"WHEN"0000100000",
"0110"WHEN"0001000000",
"0111"WHEN"0010000000",
"1000"WHEN"0100000000",
"1001"WHEN"1000000000",
"0000"WHENOTHERS;
endBehavioral;
--分频器将较高速的外部时钟频率分频成每分钟一次的时钟频率,以便进行时钟计数。
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityfq_divideris
Port(clk_in:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
clk_out:
outSTD_LOGIC);
endfq_divider;
architectureBehavioraloffq_divideris
signaltemp:
std_logic_vector(5downto0);
begin
process(reset,clk_in)
begin
ifreset='1'then
temp<="000000";
clk_out<='0';
elsifrising_edge(clk_in)then
if(temp="111011")then
temp<="000000";
clk_out<='1';
else
temp<=temp+1;
clk_out<='0';
endif;
endif;
endprocess;
endBehavioral;
--键盘缓冲器是一个移位寄存器,暂存用户键入的数字,
-------------并且实现用户键入数字在显示器上从右到左的依次显示。
-------------这里需要注意的是,由图6.23可以看出,KEY_BUFFER的时钟端连接的是外部KEY_DOWN信号。
-------------这表示用户每输入一个数字,KEY_BUFFER移位一次。
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitykey_bufferis
Port(clk:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
key:
inSTD_LOGIC_VECTOR(3downto0);
new_time1:
outSTD_LOGIC_VECTOR(3downto0);
new_time2:
outSTD_LOGIC_VECTOR(3downto0);
new_time3:
outSTD_LOGIC_VECTOR(3downto0);
new_time4:
outSTD_LOGIC_VECTOR(3downto0));
endkey_buffer;
architectureBehavioralofkey_bufferis
signalreg:
STD_LOGIC_VECTOR(15downto0):
="0000000000000000";
begin
PROCESS(clk,reset)
BEGIN
ifreset='1'then
reg<="0000000000000000";
elsIFrising_edge(clk)THEN
reg<=reg(11downto0)&key;
ENDIF;
ENDPROCESS;
new_time1<=reg(15downto12);
new_time2<=reg(11downto8);
new_time3<=reg(7downto4);
new_time4<=reg(3downto0);
endBehavioral;
--计数器实际上是一个异步复位、异步置数的累加器,
---------通常情况下进行时钟累加计数,必要时可置入新的时钟值,然后从该值开始新的计数。
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityalarm_counteris
Port(load_new_c:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
clk:
inSTD_LOGIC;
new_current_time1:
inSTD_LOGIC_VECTOR(3downto0);
new_current_time2:
inSTD_LOGIC_VECTOR(3downto0);
new_current_time3:
inSTD_LOGIC_VECTOR(3downto0);
new_current_time4:
inSTD_LOGIC_VECTOR(3downto0);
new_time1:
outSTD_LOGIC_VECTOR(3downto0);
new_time2:
outSTD_LOGIC_VECTOR(3downto0);
new_time3:
outSTD_LOGIC_VECTOR(3downto0);
new_time4:
outSTD_LOGIC_VECTOR(3downto0));
endalarm_counter;
architectureBehavioralofalarm_counteris
signaltemp1,temp2,temp3,temp4:
std_logic_vector(3downto0):
="0000";
begin
process(reset,clk,load_new_c)
begin
ifreset='1'then
temp1<="0000";
temp2<="0000";
temp3<="0000";
temp4<="0000";
--new_time1<="0000";
--new_time2<="0000";
--new_time3<="0000";
--new_time4<="0000";
elsifload_new_c='1'then
temp1<=new_current_time1;
temp2<=new_current_time2;
temp3<=new_current_time3;
temp4<=new_current_time4;
elsifrising_edge(clk)then
iftemp4="1001"then
temp4<="0000";
iftemp3="0101"then
temp3<="0000";
if(temp1="0010")and(temp2="0011")then
temp1<="0000";
temp2<="0000";
elsif(temp1<="0010")and(temp2="1001")then
temp2<="0000";
temp1<=temp1+1;
else
temp2<=temp2+1;
endif;
else
temp3<=temp3+1;
endif;
else
temp4<=temp4+1;
endif;
endif;
endprocess;
new_time1<=temp1;
new_time2<=temp2;
new_time3<=temp3;
new_time4<=temp4;
endBehavioral;
--寄存器用于保存用户设置的闹钟时间,是一个异步复位寄存器。
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityalarm_regis
Port(clk:
inSTD_LOGIC;
load_new_a:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
new_alarm_time1:
inSTD_LOGIC_VECTOR(3downto0);
new_alarm_time2:
inSTD_LOGIC_VECTOR(3downto0);
new_alarm_time3:
inSTD_LOGIC_VECTOR(3downto0);
new_alarm_time4:
inSTD_LOGIC_VECTOR(3downto0);
alarm_time1:
outSTD_LOGIC_VECTOR(3downto0);
alarm_time2:
outSTD_LOGIC_VECTOR(3downto0);
alarm_time3:
outSTD_LOGIC_VECTOR(3downto0);
alarm_time4:
outSTD_LOGIC_VECTOR(3downto0));
endalarm_reg;
architectureBehavioralofalarm_regis
begin
process(reset,clk)
begin
ifreset='1'then
alarm_time1<="0000";
alarm_time2<="0000";
alarm_time3<="0000";
alarm_time4<="0000";
elsifrising_edge(clk)then
ifload_new_a='1'then
alarm_time1<=new_alarm_time1;
alarm_time2<=new_alarm_time2;
alarm_time3<=new_alarm_time3;
alarm_time4<=new_alarm_time4;
endif;
endif;
endprocess;
endBehavioral;
--显示器根据需要显示当前时间、用户设置的闹钟时间或用户通过键盘输入的新的时间,
---------同时判断当前时间是否已到了闹钟时间,实际上是一个多路选择器加比较器。
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydisplay_driveris
Port(show_new_time:
inSTD_LOGIC;
show_a:
inSTD_LOGIC;
new_time1:
inSTD_LOGIC_VECTOR(3downto0);
new_time2:
inSTD_LOGIC_VECTOR(3downto0);
new_time3:
inSTD_LOGIC_VECTOR(3downto0);
new_time4:
inSTD_LOGIC_VECTOR(3downto0);
current_time1:
inSTD_LOGIC_VECTOR(3downto0);
current_time2:
inSTD_LOGIC_VECTOR(3downto0);
current_time3:
inSTD_LOGIC_VECTOR(3downto0);
current_time4:
inSTD_LOGIC_VECTOR(3downto0);
alarm_time1:
inSTD_LOGIC_VECTOR(3downto0);
alarm_time2:
inSTD_LOGIC_VECTOR(3downto0);
alarm_time3:
inSTD_LOGIC_VECTOR(3downto0);
alarm_time4:
inSTD_LOGIC_VECTOR(3downto0);
display1:
outSTD_LOGIC_VECTOR(3downto0);
display2:
outSTD_LOGIC_VECTOR(3downto0);
display3:
outSTD_LOGIC_VECTOR(3downto0);
display4:
outSTD_LOGIC_VECTOR(3downto0);
sound_alarm:
outstd_logic);
enddisplay_driver;
architectureBehavioralofdisplay_driveris
begin
process(show_new_time,show_a,current_time1,current_time2,current_time3,current_time4)
begin
if(current_time1=alarm_time1)and(current_time2=alarm_time2)and(current_time3=alarm_time3)and(current_time4=alarm_time4)then
sound_alarm<='1';
else
sound_alarm<='0';
endif;
endprocess;
process(show_new_time,show_a,current_time1,current_time2,current_time3,current_time4,new_time1,new_time2,new_time3,new_time4,alarm_time1,alarm_time2,alarm_time3,alarm_time4)
begin
if(show_new_time='1')then
display1<=new_time1;
display2<=new_time2;
display3<=new_time3;
display4<=new_time4;
elsif(show_a='1')then
display1<=alarm_time1;
display2<=alarm_time2;
display3<=alarm_time3;
display4<=alarm_time4;
else
display1<=current_time1;
display2<=current_time2;
display3<=current_time3;
display4<=current_time4;
endif;
endprocess;
endBehavioral;
--控制器是设计的核心部分,按设计要求产生相应的控制逻辑,以控制其他各部分的工作。
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityalarm_controlleris
Port(key:
inSTD_LOGIC;
clk:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
time_button:
inSTD_LOGIC;
alarm_button:
inSTD_LOGIC;
load_new_c:
outSTD_LOGIC;
load_new_a:
outSTD_LOGIC;
show_new_time:
outSTD_LOGIC;
show_a:
outSTD_LOGIC);
endalarm_controller;
ARCHITECTUREARTOFALARM_CONTROLLERISTYPEt_stateIS(S0,S1,S2,S3,S4);CONSTANTKEY_TIMEOUT:
std_logic_vector:
="11101";SIGNALCURR_STATE:
t_state;SIGNALNEXT_STATE:
t_state;SIGNALCOUNTER:
std_logic_vector(4downto0);SIGNALENABLE_COUNT:
STD_LOGIC;SIGNALCOUNT_END:
STD_LOGIC;
BEGIN
PROCESS(CLK,RESET)BEGINIFRESET='1'THENCURR_STATE<=S0;ELSE
IFrising_edge(clk)THENCURR_STATE<=NEXT_STATE;ENDIF;
ENDIF;ENDPROCESS;
PROCESS(KEY,ALARM_BUTTON,TIME_BUTTON,CURR_STATE,COUNT_END)BEGINNEXT_STATE<=CURR_STATE;LOAD_NEW_A<='0';LOAD_NEW_C<='0';SHOW_A<='0';SHOW_NEW_TIME<='0';ENABLE_COUNT<='0';
CASECURR_STATEISWHENS0=>IF(KEY='1')THENNEXT_STATE<=S1;SHOW_NEW_TIME<='1';ELSIF(ALARM_BUTTON='1')THENNEXT_STATE<=S4;SHOW_A<='1';ELSENEXT_STATE<=S0;ENDIF;WHENS1=>IF(KEY='1')THENNEXT_STATE<=S1;
ELSIF(ALARM_BUTTON='1')THENNEXT_STATE<=S2;LOAD_NEW_A<='1';ELSIF(TIME_BUTTON='1')THENNEXT_STATE<=S3;LOAD_NEW_C<='1';ELSEIF(COUNT_END='1')THENNEXT_STATE<=S0;ELSENEXT_STATE<=S1;ENDIF;ENABLE_COUNT<='1';ENDIF;SHOW_NEW_TIME<='1';
WHENS2=>IF(ALARM_BUTTON='1')THENNEXT_STATE<=S2;LOAD_NEW_A<='1';ELSENEXT_STATE<=S0;ENDIF;WHENS3=>IF(TIME_BUTTON='1')THENNEXT_STATE<=S3;LOAD_NEW_C<='1';ELSENEXT_STATE<=S0;
ENDIF;WHENS4=>IF(KEY='1')THENNEXT_STATE<=S1;ELSENEXT_STATE<=S4;IF(COUNT_END='1')THENNEXT_STATE<=S0;ELSENEXT_STATE<=S4;SHOW_A<='1';
ENDIF;ENABLE_COUNT<='1';ENDIF;WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;
PROCESS(ENABLE_COUNT,CLK)BEGINIF(ENABLE_COUNT='0')THENCOUNTER<="00000";COUNT_END<='0';ELSIF(RISING_EDGE(CLK))THENIF(COUNTER>=KEY_TIMEOUT)THENCOUNT_END<='1';ELSECOUNTER<=COUNTER+1;ENDIF;ENDIF;ENDPROCESS;
ENDART;
--测试文件
--------------------------------------------------------------------------------
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.all;
USEieee.n
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