华南理工大学数字系统设计全英试题A卷.docx

华南理工大学数字系统设计全英试题A卷.docx

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华南理工大学数字系统设计全英试题A卷

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华南理工大学期末考试

《数字系统设计（全英课）》试卷A（2014.1.16）

注意事项：

1.考前请将密封线内各项信息填写清楚；

2.所有答案请在试卷上答题；

3．考试形式：

闭卷；

4.本试卷共三大题，满分100分，考试时间120分钟。

题号

一

二

三

总分

得分

评卷人

1.Multiplechoicetest（2ⅹ10=20marks）

1.Whichofthefollowingstatementsisnottrue?

（D）

A．VHDLsignalassignmentneedsatimedelaytotakeeffect

B．VHDLsignalcanbedeclaredinarchitecture,it’sglobal

C．VHDLvariableassignmenttakeseffectimmediately

D．VHDLvariableisusuallydeclaredinprocess,itshouldbeincludedinsensitivitylist

2.WhichofthefollowingVHDLdatatypescanbeuseddirectly，withoutexplicitdeclaration?

（C）

A.STD_LOGIC；B.STD_LOGIC_VECTOR；C.BIT；D.ARRAY

3.WhichofthefollowingstatementsonPLDisnottrue（B）

A.CycloneIIisproducedbyAlteraB.FPGAisbasedonproductterms

C.FPGAisfieldprogrammablegatearray

4.Whichofthefollowingstatementsonsequentialcircuitistrue（B）

A.Insynchronouscircuit，theactionsofFlip-Flopsarenotnecessarilysynchronizedbythesameclocksignal

B.Inasynchronouscircuit，thestatesofFlip-Flopsdon’tchangesimultaneously

C.TheinputchangeofMoorestatemachineisdirectlyreflectedbyoutput

5.Whichofthefollowingstatementsonstatemachinedescriptionisnottrue（C）

A．Inone-processdescriptionstyle,outputcanbesynchronized

B.Two-processdescriptionstylecanavoidunwantedregisters

C.Two-processdescriptionstyleconsumesmoreresourcesthanone-processdescription

6.Whichofthefollowingstatementsonmetastabilityistrue（B）

A.Insequentialcircuit,metastabilitydoesn’toccurifeithertheset-uptimerequirementortheholdingtimerequirementismet.

B.Metastabilitydoesn’tnegativelyimpactthesystemifthemetastableoutputresolvestothenormalstatebeforeitiscapturedbythenextregister.

C.Metastabilityusuallyoccursinsynchronouscircuit.

7.WhichofthefollowingstatementsonVHDLsignalisnottrue（C）

A.VHDLsignalisusuallysynthesizedasnodeorwire.

B.InVHDLentity,portisconsideredassignalbydefault

C.Assignmenttothesamesignalindifferentprocessescanbesynthesized,butonlyonesignalassignmenttakeseffect.

8.Forstateencodinginstatemachine,whichofthefollowingschemeismoresimplefordecodingatthepricesofmoreFlip-Flopsinencoding:

（A）

A.onehotcodeB.NaturalbinarycodeC.Graycode

9.WhichofthefollowingstatementsonVHDLcasestatementisnottrue（B）

A.Eachbranchofcasestatementshouldbecorrespondingtooneorseveralpossiblevaluesoftheevaluatedexpression.

B.Statement“WHENOTHERS=>NULL”mustbeincludedincasestatement

C.Inexecutionofcasestatement，onlyonebranchisselected

10.Whichofthefollowingstatementsisnotconcurrent?

（B）

A.processstatementB.CASEstatement

C.componentinstantiationD.WHEN…ELSE…statement

2.Shortanswerquestions（5ⅹ4=20marks）

1、PleasespecifythebasiccomponentsofASMchart,particularly,explainwhatastateis.

BasiccomponentsofASMchart:

statebox,decisionbox,andconditionaloutputbox.

Onestateismorethanastatebox,conditionaloutputbox,ordecisionboxcanalsobeapartofthestate.Astaterepresentsthesystemstateduringoneclockcycle,indicatingtheoperationstobedoneinthestate.

2、Whatisthedifferencebetweensequentiallogiccircuitandcombinationallogiccircuit?

Combinationalcircuit:

changesininputsareimmediatelyreflectedbychangesinoutput.Thestableoutputdependsonthecurrentinputonly.

Theoutputsofasystemdependonpastvaluesofitsinputsaswellasthepresentstatevalues.（dependonbothpresentstateandhistorystate）

3、Pleasespecifythebasicstructureofsequentiallogiccircuit

Structure:

itiscomposedofcombinationallogicgates,andmemorycomponentssuchasFlip-flop,registers.

4、Pleasedescribetheconceptofset-uptimeandholdingtime.

Setuptime：

Toensurereliableoperation,theinputtoaregistermustbestableforaminimumtimebeforetheclockedge（registersetuptimeortSU）.ifthetimeisnotlongenough,reliableoperationcannotbeguaranteed.

Holdtime：

Toensurereliableoperation,theinputtoaregistermustbestableforaminimumtimeaftertheclockedge（registerholdtimeortH）.ifthetimeisnotlongenough,reliableoperationcannotbeguaranteed.

3、Comprehension&design（60marks）

1、UsingVHDL,Pleasedescribeatri-statemultiplexer（MUX）accordingtothefollowingrequirements:

（10marks）

input

output

oe

a

b

sel

y

1

a

b

0

a

1

b

0

-

‘Z’

LIBRARYIEEE；

USEIEEE.std_logic_1164.ALL;

ENTITYMUXIS

PORT（oe,a,b,sel:

instd_logic;

y:

outstd_logic）;

ENDMUX;

ARCHITECTUREBEHAVOFMUXIS

BEGIN

PROCESS（oe,a,b,sel）

BEGIN

Ifoe=’1’then

ifsel=’0’then

y<=a;

else

y<=b;

endif;

else

y<=’Z’;

endif;

ENDPROCESS:

ENDARCHITECTURE;

2、Asapartoftestbench,pleasedescribethefollowingstimuli（6marks）

…

SignalS1：

std_logic;

SignalS2：

std_logic;

…

Process

Begin

S1<=’0’;

Waitfor10ns;

S1<=’1’;

Waitfor5ns;

S1<=’0’;

Waitfor10ns;

Endprocess;

Process

Begin

S1<=’0’;

Waitfor5ns;

S1<=’1’;

Waitfor15ns;

S1<=’0’;

Waitfor5ns;

Endprocess;

3、PleasedrawtheRTLdiagramforthefollowingVHDLcodes（5marks）

entityvar_sigis

port（data:

inbit_vector（1downto0）;clk:

inbit;z:

outbit）;

constantk1:

bit_vector:

=“01”;

constantk2:

bit_vector:

=“10”;

endvar_sig;

architectureAofvar_sigis

begin

var:

process

variablea1,a2:

bit_vector（1downto0）;

variablea3:

bit;

begin

waituntilclk=‘1’andclk’event;

a1:

=dataandk1;

a2:

=dataandk2;

a3:

=a1（0）ora2

（1）;

z<=a3;

endprocessvar;

endA

4、PleasecompletethewaveformsaccordingtothefollowingVHDLcodes（6marks）

Libraryieee;

Useieee.std_logic_1164.all;

EntityD_latchis

port（D,Enable:

instd_logic;

Q1，Q2:

outstd_logic）;

EndD_latch;

ArchitecturebehavofD_latchis

Begin

process（D,Enable）

begin

if（Enable=‘1’）thenQ1<=D;

endif;

endprocess;

process（Enable）

begin

if（Enable=‘1’）thenQ2<=D;

endif;

endprocess;

Endbehav;

5、Designa4-bitALU（ArithmeticLogicUnit）,whichcancompletethefollowingoperationson4-bitinputsaandb:

1）

Mode1:

Addition（a+b）

Mode2:

OR（aorb）

Mode3:

AND（aandb）

Mode4:

XOR（axorb）

2）TheworkingmodeoftheALUdependsonthemodeinputM0andM1.Forexample:

M0M1

MODE

00

addition

01

OR

10

AND

11

XOR

3）Theadditionoperationshouldhavecarried-inbitandcarried-outbit

Questions:

（13marks）

1.PleaseindicatetheinputsandoutputsoftheALU

Inputs:

a,b,M0,M1,ci

Ouput:

s,co

2.PleasefinishVHDLdesignofALU，includingentityandarchitecturedescription.

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

EntityALUis

port（a,b:

instd_logic_vector（3downto0）;

m0,m1,ci:

instd_logic;

s:

outstd_logic_vector（3downto0）;

co:

instd_logic;）;

endALU;

architecturebehavofALUis

signalmode:

std_logic_vector（1downto0）;

begin

mode<=m1&m0;

process

variabletemp1,temp2,temp3:

std_logic_vector（4downto0）;

begin

ifmode=”00”then

temp1:

=0&a;

temp2:

=0&b;

temp3:

=temp1+temp2+ci;

co=temp3（4）;

s<=temp3（3downto0）;

elsifmode=”01”then

s<=aorb;

elsifmode=”10”then

s<=aandb;

elsifmode=”11”then

s<=axorb;

else

s<=”ZZZZ”;

co<=’Z’;

endif;

endprocess;

endarchitecture;

6.Pleasereadeachpieceofthefollowingcodescarefully.Doeseachofthemhavethesamecircuitbehaviorlikethefollowingcircuitdiagram?

Ifno,pleasegivethereasons.（9marks）

（a）

process

begin

waituntilrising_edge（clk）;

d<=notc;

c<=aandb;

endprocess;

（b）

process

begin

waituntilrising_edge（clk）;

c1<=aandb;

c2<=notc1;

d<=c2;

endprocess;

（c）

process

begin

waituntilrising_edge（clk）;

c1<=aandb;

d<=c2;

endprocess;

process（c1）

begin

c2<=notc1;

endprocess;

（a）yes:

（b）no:

extraregisterisintroduced.

（c）yes

7、Designaserialdatatransmitter（串行数据发送器）。

Paralleldatainput‘Z’of8bitsisloadedfirstlyinthetransmitter,andseriallytransmittedthroughport‘X’.Thedetailedrequirementsarelistedasfollows:

a）Inputsignal‘load’isusedforparalleldataloading.Ifload=’1’,paralleldatainput‘Z’isloadedintheserialtransmitter,andoutputsignal‘empty’=’0’toturnofftheLED;

b）Leastsignificantbit（最低位）istransmittedfirstly;

c）Astartbitoflogic‘0’（起始位0）istransmittedfirstlybeforethe8-bitrealdatatransmission;

d）Aparitybit（奇偶效验位）andstopbitoflogic‘1’（停止位1）aretransmittedafterthe8–bitrealdatatransmission;

e）Afterthetransmissionofthestopbit,outputsignal‘empty’=’1’toturnontheLED;

Question:

（11marks）

1.Pleasespecifytheportinformation.

Input:

Output:

2.PleasedrawanASMchartfortheserialtransmitter.