用状态机实现的EDA多功能数字钟课程设计VHDL代码.docx

用状态机实现的EDA多功能数字钟课程设计VHDL代码.docx

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用状态机实现的EDA多功能数字钟课程设计VHDL代码

设计并实现具有一定功能的数字钟

1、该数字钟可以实现3个功能：

计时功能、整点报时功能和重置时间功能，因此有3个功能：

计时、重置时间、复位。

2、对所有设计的小系统能够正确分析；

3、基于VHDL语言描述系统的功能；

4、在quartus2环境中编译通过；

5、仿真通过并得到正确的波形；

6、给出相应的设计报告。

其中计时模块有4部分构成：

秒计时器（second）、分计时器（minute）、时计时器（hour）、日计时器（date）、月计时器（mouth）、年计时器（year）

1）秒计时器（second）是由一个60进制的计数器构成的，具有清0、置数和计数功能。

其中reset为清0信号，当reset为0时，秒计时器清0；set为置数信号，当set为0时，秒计时器置数，置s1的值。

clk为驱动秒计时器的时钟，sec为秒计时器的输出，ensec为秒计时器的进位信号，作为下一级的时钟输入信号。

2）分计时器（minute）是由一个60进制的计数器构成的，具有清0、置数和计数功能。

其中reset为清0信号，当reset为0时，分计时器清0；set为置数信号，当set为0时，分计时器置数，置m1的值。

clkm为驱动分计时器工作的时钟，与ensec相连接；min为分计时器的输出；enmin为分计时器的进位信号，作为下一级的时钟输入信号。

3）时计时器（hour）是由一个24进制的计数器构成的，具有清0、置数和计数功能。

其中reset为清0信号，当reset为0时，时计时器清0；set为置数信号，当set为0时，时计时器置数，置h1的值。

clkh为驱动时计时器工作的时钟，与enmin相连接；hour为时计时器的输出；enhour为时计时器的进位信号，作为下一级的时钟输入信号。

4）日计时器（date1）是由一个60进制的计数器构成的，具有清0、置数和计数功能。

其中reset为清0信号，当reset为0时，星期计时器清0；set为置数信号，当set为0时，星期计时器置数，置d1的值。

clkd为驱动星期计时器工作的时钟，与enhour相连接；date为日计时器的输出，endate为分计时器的进位信号，作为下一级的时钟输入信号，由于月份的天数存在天数不同，闰年2月的天数为28天等情况，还设计了一个润年判别器，准确显示时间。

5）月计时器（mouth）是由一个60进制的计数器构成的，具有清0、置数和计数功能。

其中reset为清0信号，当reset为0时，星期计时器清0；set为置数信号，当set为0时，星期计时器置数，置mou1的值，clkmou为驱动星期计时器工作的时钟，与enday相连接；mou为日计时器的输出，enmou为分计时器的进位信号，作为下一级的时钟输入信号。

6）计时器（year）是由一个60进制的计数器构成的，具有清0、置数和计数功能。

其中reset为清0信号，当reset为0时，星期计时器清0；set为置数信号，当set为0时，星期计时器置数，置y1的值，clky为驱动星期计时器工作的时钟，与enmou相连接；year为日计时器的输出。

VHDL程序

1、屏幕切换模块

运用状态机进行屏幕切换，分别显示年月日，以及时分秒

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitymux3is

Port（clk,Reset,sel:

instd_logic;

int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:

INSTD_LOGIC_VECTOR（3DOWNTO0）;--rstmust

a1,a2,a3,a4,a5,a6:

outstd_logic_vector（3downto0））;

endmux3;

architectureBehavioralofmux3is

TYPEstatesIS（st0,st1,st2,st3,st4,st5,st6,st7）;

SIGNALSTX:

states;

begin

COM1:

PROCESS（STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12）

BEGIN--决定转换状态的进程

CASESTXIS

WHENst0=>a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHENst1=>a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHENst2=>a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHENst3=>a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHENst4=>a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12;

WHENst5=>a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHENst6=>a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHENst7=>a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

WHENOTHERS=>NULL;

ENDCASE;

ENDPROCESSCOM1;

REG:

PROCESS（clk,Reset,sel）--主控时序进程

BEGIN

IFReset='1'THENSTX<=st0;--异步复位

ELSIFclk='1'ANDclk'EVENTTHEN

ifsel='1'then

CASESTXIS

WHENst0=>STX<=st1;

WHENst1=>STX<=st2;

WHENst2=>STX<=st3;

WHENst3=>STX<=st4;

WHENst4=>STX<=st5;

WHENst5=>STX<=st6;

WHENst6=>STX<=st7;

WHENst7=>STX<=st0;

ENDCASE;

ENDIF;

ENDif;

ENDPROCESS;

2、显示切换程序

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitymux1is

Port（clk,ina,inb,sel,Reset:

instd_logic;

result:

outstd_logic）;

endmux1;

architectureBehavioralofmux1is

TYPEstateIS（st0,st1,st2,st3,st4,st5,st6,st7）;

SIGNALSTX:

state;

begin

REG1:

PROCESS（ina,inb,STX）

BEGIN

CASESTXIS

WHENst0=>result<=ina;

WHENst1=>result<=ina;

WHENst2=>result<=inb;

WHENst3=>result<=inb;

WHENst4=>result<=inb;

WHENst5=>result<=inb;

WHENst6=>result<=inb;

WHENst7=>result<=inb;

ENDCASE;

ENDPROCESS;

REG2:

PROCESS（clk,sel,Reset）

BEGIN

IF（Reset='1'）THEN

STX<=st0;

ELSIF（clk'EVENTANDclk='1'）THEN

ifsel='1'then

CASESTXIS

WHENst0=>STX<=st1;

WHENst1=>STX<=st2;

WHENst2=>STX<=st3;

WHENst3=>STX<=st4;

WHENst4=>STX<=st5;

WHENst5=>STX<=st6;

WHENst6=>STX<=st7;

WHENst7=>STX<=st0;

ENDCASE;

ENDIF;

endif;

ENDPROCESSREG2;

endBehavioral;

3、置数操作模块

运用状态机，进行置数操作

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitymuxis

Port（clk,ina,inb,sel,Reset:

instd_logic;

r1,r2,r3,r4,r5,r6:

outstd_logic）;

endmux;

architectureBehavioralofmuxis

TYPEstateIS（st0,st1,st2,st3,st4,st5,st6,st7）;

SIGNALSTX:

state;

begin

PROCESS（ina,inb,STX）

BEGIN

CASESTXIS

WHENst0=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';

WHENst1=>r1<=ina;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';

WHENst2=>r1<='0';r2<='0';r3<='0';r4<='0';r5<='0';r6<=inb;

WHENst3=>r1<='0';r2<='0';r3<='0';r4<='0';r5<=inb;r6<='0';

WHENst4=>r1<='0';r2<='0';r3<='0';r4<=inb;r5<='0';r6<='0';

WHENst5=>r1<='0';r2<='0';r3<=inb;r4<='0';r5<='0';r6<='0';

WHENst6=>r1<='0';r2<=inb;r3<='0';r4<='0';r5<='0';r6<='0';

WHENst7=>r1<=inb;r2<='0';r3<='0';r4<='0';r5<='0';r6<='0';

ENDCASE;

ENDPROCESS;

PROCESS（clk,sel,Reset）

BEGIN

IF（Reset='1'）THEN

STX<=st0;

ELSIF（clk'EVENTANDclk='1'）THEN

ifsel='1'then

CASESTXIS

WHENst0=>STX<=st1;

WHENst1=>STX<=st2;

WHENst2=>STX<=st3;

WHENst3=>STX<=st4;

WHENst4=>STX<=st5;

WHENst5=>STX<=st6;

WHENst6=>STX<=st7;

WHENst7=>STX<=st0;

ENDCASE;

ENDIF;

endif;

ENDPROCESS;

endBehavioral;

endBehavioral;

4、秒显示模块

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitysecute1is

Port（clkm,set,reset:

instd_logic;

sec2,sec1:

inoutstd_logic_vector（3downto0）;

ensec:

outstd_logic）;

endsecute1;

architectureBehavioralofsecute1is

begin

Process（clkm,reset,set）

Begin

Ifreset='1'thensec2<="0000";sec1<="0000";

Elsifset='1'thensec2<="0101";sec1<="1000";

Elsif（clkm'eventandclkm='1'）then

ifsec2="0101"ANDsec1="1001"thensec2<="0000";sec1<="0000";ensec<='1';

elsifsec1="1001"thensec2<=sec2+'1';sec1<="0000";ensec<='0';

elsesec1<=sec1+'1';ensec<='0';

endif;

endif;

Endprocess;

endBehavioral;

5、分显示模块

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entityminute1is

Port（clkm,set,reset:

instd_logic;

min2,min1:

inoutstd_logic_vector（3downto0）;

enmin:

outstd_logic）;

endminute1;

architectureBehavioralofminute1is

begin

Process（clkm,reset,set）

Begin

Ifreset='1'thenmin2<="0000";min1<="0000";

Elsifset='1'thenmin2<="0101";min1<="1000";

Elsif（clkm'eventandclkm='1'）then

ifmin2="0101"ANDmin1="1001"thenmin2<="0000";min1<="0000";enmin<='1';

elsifmin1="1001"thenmin2<=min2+'1';min1<="0000";enmin<='0';

elsemin1<=min1+'1';enmin<='0';

endif;

endif;

Endprocess;

endBehavioral;

6、小时显示模块

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entityhour1is

Port（clkh,set,reset:

instd_logic;

hor2,hor1:

inoutstd_logic_vector（3downto0）;

enhour:

outstd_logic）;

endhour1;

architectureBehavioralofhour1is

begin

Process（clkh,reset,set）

Begin

Ifreset='1'thenhor2<="0000";hor1<="0000";

Elsifset='1'thenhor2<="0010";hor1<="0011";

Elsif（clkh'eventandclkh='1'）then

ifhor2="0010"ANDhor1="0011"thenhor2<="0000";hor1<="0000";enhour<='1';

elsifhor1="1001"thenhor2<=hor2+'1';hor1<="0000";enhour<='0';

elsehor1<=hor1+'1';enhour<='0';

endif;

endif;

Endprocess;

endBehavioral;

7、日显示模块（已加入闰年判断功能）

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitydate1is

Port（clkd,set:

instd_logic;

dat2,dat1:

inoutstd_logic_vector（3downto0）;

endate:

outstd_logic）;

enddate1;

architectureBehavioralofdate1is

begin

Process（clkd,set）

Begin

ifset='1'thendat2<="0010";dat1<="1000";

Elsif（clkd'eventandclkd='1'）then

ifdat2="0011"ANDdat1="0000"thendat2<="0000";dat1<="0001";endate<='1';

elsifdat1="1001"thendat2<=dat2+'1';dat1<="0000";endate<='0';

elsedat1<=dat1+'1';endate<='0';

endif;

endif;

Endprocess;

endBehavioral;

8、月显示模块

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitymonth1is

Port（clkn,set:

instd_logic;

mon2,mon1:

inoutstd_logic_vector（3downto0）;

enmon:

outstd_logic）;

endmonth1;

architectureBehavioralofmonth1is

begin

Process（clkn,set）

Begin

ifset='1'thenmon2<="0000";mon1<="0110";

Elsif（clkn'eventandclkn='1'）then

ifmon2="0001"ANDmon1="0010"thenmon2<="0000";mon1<="0001";enmon<='1';

elsifmon1="1001"thenmon2<=mon2+'1';mon1<="