EDA复习.docx
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EDA复习.docx
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EDA复习
2输入与门
程序清单如下:
entityAND2Ais
port(A,B:
inbit;
C:
outbit);
endentityAND2A;
architectureEX1ofAND2Ais
begin
C<=AandB;
endarchitectureEX1;
3输入与非门
程序清单如下:
entityNAND3Ais
port(A,B,C:
inbit;
Y:
outbit);
endentityNAND3A;
architectureEX2ofNAND3Ais
begin
Y<=not(AandBandC);
endarchitectureEX2;
一位全加器
程序清单如下:
entityAND4Ais
port(a,b,ci:
inbit;s,co:
outbit);
endentityAND4A;
architectureEX4ofAND4Ais
begin
s<=axorbxorci;
co<=((axorb)andci)or(aandb);
endarchitectureEX4;
高电平使能有效的三态非门
程序清单如下:
libraryieee;
useieee.std_logic_1164.all;
entityAND5Ais
port(a,en:
instd_logic;y:
outstd_logic);
endentityAND5A;
architectureEX5ofAND5Ais
begin
process(a,en)
begin
ifen='1'
theny<=nota;
elsey<='Z';
endif;
endprocess;
endEX5;
2选1数据选择器
程序清单:
libraryieee;
useieee.std_logic_1164.all;
entityMUX21Ais
port(D1,D0,A,EN:
instd_logic;
Y:
outstd_logic);
endentityMUX21A;
architectureoneofMUX21Ais
begin
Y<=D0whenA='0'andEN='1'
elseD1whenA='1'andEN='1'
else'Z';
endarchitectureone;
仿真波形:
4选1数据选择器
程序清单:
libraryieee;
useieee.std_logic_1164.all;
entityMUX41Ais
port(EN,D3,D2,D1,D0,A1,A0:
instd_logic;
Y:
outstd_logic);
endentityMUX41A;
architectureoneofMUX41Ais
begin
Y<=D0whenA1='0'andA0='0'andEN='0'
elseD1whenA1='0'andA0='1'andEN='0'
elseD2whenA1='1'andA0='0'andEN='0'
elseD3whenA1='1'andA0='1'andEN='0'
else'Z';
endarchitectureone;
仿真波形:
8选1数据选择器
程序清单:
libraryieee;
useieee.std_logic_1164.all;
entityMUX81Ais
port(EN,D7,D6,D5,D4,D3,D2,D1,D0,A2,A1,A0:
instd_logic;
Y:
outstd_logic);
endentityMUX81A;
architectureoneofMUX81Ais
begin
Y<=D0whenA2='0'andA1='0'andA0='0'andEN='0'
elseD1whenA2='0'andA1='0'andA0='1'andEN='0'
elseD1whenA2='0'andA1='1'andA0='0'andEN='0'
elseD1whenA2='0'andA1='1'andA0='1'andEN='0'
elseD1whenA2='1'andA1='0'andA0='0'andEN='0'
elseD1whenA2='1'andA1='0'andA0='1'andEN='0'
elseD1whenA2='1'andA1='1'andA0='0'andEN='0'
elseD1whenA2='1'andA1='1'andA0='1'andEN='0'
else'Z';
endarchitectureone;
仿真波形:
8选1数据选择器的VHDL设计(低电平使能端)
1.实体框图
2.程序设计
libraryieee;
useieee.std_logic_1164.all;
entitymux81ais
port(A0,A1,A2,D0,D1,D2,D3,D4,D5,D6,D7,EN:
instd_logic;
y:
outstd_logic);
endmux81a;
architecturebbbofmux81ais
signalA:
std_logic_vector(2downto0);
begin
A<=A2&A1&A0;
y<=D0whenA="000"andEN='0'else
D1whenA="001"andEN='0'else
D2whenA="010"andEN='0'else
D3whenA="011"andEN='0'else
D4whenA="100"andEN='0'else
D5whenA="101"andEN='0'else
D6whenA="110"andEN='0'else
D7whenA="111"andEN='0'
else'Z';
endarchitecturebbb;
3.仿真波形图
4.仿真波形分析
D0-D7是数据输入端,EN为使能端,低电平有效,A2,A1,A0是控制输入端,Y是数据输出端。
当A2、A1、A0=‘000’时,D0数据被选中,输出Y=D0;当A2、A1、A0=‘001’时,D1数据被选中,输出Y=D1,当A2、A1、A0=‘010’时,D2数据被选中,输出Y=D2,当A2、A1、A0=‘011’时,D3数据被选中,输出Y=D3,当A2、A1、A0=‘100’时,D4数据被选中,输出Y=D4,当A2、A1、A0=‘101’时,D5数据被选中,输出Y=D5,当A2、A1、A0=‘110’时,D6数据被选中,输出Y=D6,当A2、A1、A0=‘111’时,D7数据被选中,输出Y=D7。
std_logic_vector是标准逻辑矢量,定义的是长度大于1的变量,需要确定赋值方向(ndownto0)or(0downton)。
std_logic是长度为1的逻辑与bit相似,只是bit只能是'0’和'1‘而std_logic有以下九种状态:
U'——初始值,'X'——不定,'0'——0,'1'——1,'Z'——高阻,'W'——弱信号不定,'L'——弱信号0,'H'——弱信号1,'-'——不可能的情况
38译码器:
用WITH-SELECT语句(低电平有效输出):
程序清单:
libraryieee;
useieee.std_logic_1164.all;
entityDECODER38Ais
port(A2,A1,A0,S3,S2,S1:
instd_logic;
Y:
outstd_logic_vector(7downto0));
endDECODER38A;
architectureaaaofDECODER38Ais
signalF:
std_logic_vector(5downto0);
begin
F<=S3&S2&S1&A2&A1&A0;
withFselect
Y<="11111110"when"001000",
"11111101"when"001001",
"11111011"when"001010",
"11110111"when"001011",
"11101111"when"001100",
"11011111"when"001101",
"10111111"when"001110",
"01111111"when"001111",
"ZZZZZZZZ"whenothers;
endaaa;
仿真波形:
用WHEN-ELSE语句(高电平有效输出):
程序清单:
libraryieee;
useieee.std_logic_1164.all;
entityDECODER38Ais
port(A2,A1,A0,S3,S2,S1:
instd_logic;
Y:
outstd_logic_vector(7downto0));
endDECODER38A;
architectureaaaofDECODER38Ais
signalF:
std_logic_vector(5downto0);
begin
F<=S3&S2&S1&A2&A1&A0;
Y<="00000001"whenF<="001000"
else"00000010"whenF<="001001"
else"00000100"whenF<="001010"
else"00001000"whenF<="001011"
else"00010000"whenF<="001100"
else"00100000"whenF<="001101"
else"01000000"whenF<="001110"
else"10000000"whenF<="001111"
else"ZZZZZZZZ";
endaaa;
仿真波形
用if语句设计一个带同步清零(低电平有效)和异步置数(高电平有效)端的D触发器。
1.程序清单如下:
libraryieee;
useieee.std_logic_1164.all;
EntityD_FFis
port(D,clk,Reset,set:
instd_logic;
Q:
outstd_logic);
EndEntityD_FF;
ArchitectureoneofD_FFis
signalQ1:
std_logic;
Begin
process(clk,Reset,set)
Begin
ifset='1'then
Q1<='1';
Else
ifclk'eventandclk='1'then
ifReset='0'then
Q1<='0';
else
Q1<=D;
endif;
endif;
endif;
endprocess;
Q<=Q1;
Endarchitectureone;
2.仿真波形:
Libraryieee;
使用if语句和case语句设计一个带异步清零(高电平有效)和同步置数(低电平有效)端的JK触发器。
1.程序清单:
useieee.std_logic_1164.all;
EntityJK_FFis
port(clk,reset,set:
instd_logic;
JK:
instd_logic_vector(0to1);
Q:
outstd_logic);
EndentityJK_FF;
ArchitecturetwoofJK_FFis
signalQ1:
std_logic;
begin
process(clk,reset,set,JK)
begin
ifreset='1'then
Q1<='0';
else
ifclk'eventandclk='1'then
ifset='0'then
Q1<='1';
else
caseJKis
when"00"=>Q1<=Q1;
when"01"=>Q1<='0';
when"10"=>Q1<='1';
when"11"=>Q1<=notQ1;
whenothers=>NULL;
endcase;
endif;
endif;
endif;
endprocess;
Q<=Q1;
endarchitecturetwo;
2.仿真波形
设计含并行置位功能的8位右移移位寄存器(时钟上升沿触发,最高位补‘0’,最低位串行输出)。
1.程序清单如下:
libraryieee;
useieee.std_logic_1164.all;
entityshiftis
port(CLK,LOAD:
instd_logic;
DIN:
instd_logic_vector(7downto0);
reg8:
instd_logic_vector(7downto0);
QB:
outstd_logic_vector(7downto0));
endshift;
architecturebehavofshiftis
begin
process(CLK,LOAD)
variablereg8:
std_logic_vector(7downto0);
begin
ifCLK'eventandCLK='1'then
ifLOAD='1'thenreg8:
=DIN;
elsereg8(6downto0):
=reg8(7downto1);
reg8(7):
='0';
endif;
endif;
QB<=reg8;
endprocess;
endbehav;
2.仿真波形
四位双向移位寄存器,并行置数,左移地位补1,右移高位补0。
1.程序清单:
libraryieee;
useieee.std_logic_1164.all;
entityshift4ais
port(clk:
instd_logic;
s:
instd_logic_vector(1downto0);
d:
instd_logic_vector(3downto0);
Q:
outstd_logic_vector(3downto0));
endshift4a;
architectureoneofshift4ais
signalQQ:
std_logic_vector(3downto0);
beginprocess(clk)begin
ifclk'eventandclk='1'then
casesis
when"11"=>QQ<=d;
when"10"=>QQ<=QQ(2downto0)&'1';
when"01"=>QQ<='0'&QQ(3downto1);
whenothers=>null;
endcase;
endif;
endprocess;
Q<=QQ;
endone;
2.仿真波形:
64进制计数器(六位2进制)
1.程序清单:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycdu_64ais
port(clk:
instd_logic;
q:
outstd_logic_vector(5downto0));
endcdu_64a;
architectureaaofcdu_64ais
signalcout2,cout1:
std_logic_vector(3downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
if(cout2=3andcout1=15)thencout2<="0000";
cout1<="0000";
elseif(cout1=15)thencout2<=cout2+1;cout1<="0000";
elsecout2<=cout2;cout1<=cout1+1;
endif;
endif;
endif;
endprocess;
q<=cout2&cout1;
endaa;
2.仿真波形:
64进制BCD码计数器。
1.程序清单:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycdu64ais
port(clk:
instd_logic;
q1,q2:
outstd_logic_vector(3downto0));
endcdu64a;
architecturethreeofcdu64ais
signalcout2,cout1:
std_logic_vector(3downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
if(cout2=6andcout1=3)thencout2<="0000";
cout1<="0000";
elseif(cout1=9)thencout2<=cout2+1;
cout1<="0000";
elsecout2<=cout2;
cout1<=cout1+1;
endif;
endif;
endif;
endprocess;
q2<=cout2;
q1<=cout1;
endthree;2.仿真波形:
十进制计数器,高电平使能信号,低电平异步清零,低电平同步置数。
1.程序清单:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt10is
port(clk,set,en,clr:
instd_logic;
d:
instd_logic_vector(3downto0);
cq:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endcnt10;
architectureoneofcnt10is
begin
process(clk,set,clr,en)
variablecqi:
std_logic_vector(3downto0);
begin
ifclr='0'thencqi:
=(others=>'0');
elsifclk'eventandclk='1'then
ifset='0'thencqi:
=d;
elsifen='1'then
ifcqi<9thencqi:
=cqi+1;
elsecqi:
=(others=>'0');
endif;
endif;
endif;
ifcqi=9thencout<='1';
elsecout<='0';
endif;
cq<=cqi;
endprocess;
endone;
2.仿真波形:
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