超大规模集成电路第九次作业秋段成华.docx
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超大规模集成电路第九次作业秋段成华.docx
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超大规模集成电路第九次作业秋段成华
Assignment9
1.Designan8-bitupanddownsynchronouscounterinVHDLwiththefollowingfeatures:
(1)Thesameportsareusedforsignalstobeinputtedandoutputted.Theportsarebi-directionallybuffered(three-state).
(2)Thecounteriswithanasynchronousresetthatassignsaspecificinitialvalueforcounting.
(3)Thecounteriswithasynchronousdataloadcontrolinputforanewvalueofcountingandanenablecontrolinputforallowingtheupanddowncounting.Theloadcontrolinputhasapriorityovertheenablecontrolinput.Thisimpliesthatwhentheloadoperationisinprocessthecounteroperationisprohibited.
(4)Somedatatypes,suchasSTD_LOGIC,UNSIGNED,SIGNEDandINTEGER,maybeused.
Synthesizethedesign.Createasetofreasonableinputwaveformsforyourdesignandcompletebothbehavioralandpost-place&routesimulationswithinternalsignalsand/orvariablesincludedinwaveformorlistwindows.
Solution:
代码如下:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitycount_8_bidiris
Port(
clk:
inSTD_LOGIC;
rst:
inSTD_LOGIC;
load:
inSTD_LOGIC;
enable:
inSTD_LOGIC;
cnt:
inoutSTD_LOGIC_VECTOR(7downto0));
endcount_8_bidir;
architectureBehavioralofcount_8_bidiris
signalcnt_in:
STD_LOGIC_VECTOR(7downto0);
signalcnt_out:
STD_LOGIC_VECTOR(7downto0);
begin
pro0:
process(oe,cnt_out,cnt)
begin
if(load='1')then
cnt<=(others=>'Z');
cnt_in<=cnt;
else
cnt<=cnt_out;
endif;
endprocess;
pro1:
process(clk,rst)
begin
if(rst='1')then
cnt_out<=(others=>'0');
elsifrising_edge(clk)then
if(load='1')then
cnt_out<=cnt_in;
elsif(enable='1')then
cnt_out<=cnt_out+1;
else
cnt_out<=cnt_out-1;
endif;
endif;
endprocess;
endBehavioral;
解释代码:
这里有两个进程,进程0时是用来控制三态门控制的双向端口。
当cnt作为输入时(load='1'),把cnt赋给cnt_in(初值装载),然后置cnt为高阻状态;否则,即cnt作为输出时(load='0'),把cnt_out(计数器计数输出值)赋给cnt。
进程1的作用是:
当复位信号rst='1',计数器输出cnt_out为全0,否则在时钟的上升沿检测cnt端口是作为输入还是作为输出,当作为输入时(load='1'),把cnt_in中的数取进来,然后当up_down='0'时,进行加法运算,否则做减法运算,同时可以和进程0配合当load='0',将数值从cnt_out输出到cnt。
TestBench代码:
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.all;
USEieee.numeric_std.ALL;
ENTITYcount_8_bidir_tbIS
ENDcount_8_bidir_tb;
ARCHITECTUREbehaviorOFcount_8_bidir_tbIS
--ComponentDeclarationfortheUnitUnderTest(UUT)
COMPONENTcount_8_bidir
PORT(
oe:
INstd_logic;
clk:
INstd_logic;
rst:
INstd_logic;
load:
INstd_logic;
enable:
INstd_logic;
cnt:
INOUTstd_logic_vector(7downto0)
);
ENDCOMPONENT;
--Inputs
signaloe:
std_logic:
='0';
signalclk:
std_logic:
='0';
signalrst:
std_logic:
='0';
signalload:
std_logic:
='0';
signalenable:
std_logic:
='0';
--BiDirs
signalcnt:
std_logic_vector(7downto0);
--Clockperioddefinitions
constantclk_period:
time:
=100ns;
BEGIN
--InstantiatetheUnitUnderTest(UUT)
uut:
count_8_bidirPORTMAP(
oe=>oe,
clk=>clk,
rst=>rst,
load=>load,
enable=>enable,
cnt=>cnt
);
--Clockprocessdefinitions
clk_process:
process
begin
clk<='0';
waitforclk_period/2;
clk<='1';
waitforclk_period/2;
endprocess;
--Stimulusprocess
stim_proc:
process
begin
rst<='1';
load<='0';
enable<='1';
cnt<=(others=>'Z');
waitfor100ns;
rst<='0';
waitfor500ns;
load<='1';
cnt<="11000000";
waitfor200ns;
load<='0';
cnt<=(others=>'Z');
waitfor500ns;
enable<='0';
waitfor500ns;
rst<='1';
wait;
endprocess;
END;
根据TestBench的激励可以看出:
进入程序之后,首先复位且load<='0',这时cnt_out从0开始做加法运算,当计数到5之后,load<='1'把cnt变成了输入,并且给其赋了"11000000"(转化为整数为192),并且在上升沿条件下送到cin_out,此时cin_out=192;在加载该值之后,200ns之后将load<='0'将cnt变为输出,此时cnt开始从192向上计数,记了经过500ns记到了197,然后遇到了enable='0',开始做减法,经过500ns,cnt变为192,随后rst='1',将cnt清0,到此结束,功能验证为正确。
后仿真波形如上所示,与行为仿真的差别,就是前面几百ps增加了一个Unknown状态(没有初始化的缘故),同时cnt相对于时钟沿有延迟。
2.FortheVHDLmodelgivenbelow(CodeListOne),comparetheFIFOsimplementationsonCPLDandFPGA.
(1)Synthesizeandverify(simulate)theVHDLdesignoftheFIFOs;
综合后的RTLschematic和功能仿真后的结果分别如下图1和图2所示。
图1
图2
(2)ForCPLDimplementation(fit)oftheFIFOs,howmanyMCs(macrocells)andPTs(productterms)areneeded?
Whichparameteriscriticaltothemaximuminternalclockworkingfrequency?
Trytofindoutthiscriticalparameteranditscorrespondingcircuitpath.
设置芯片为CoolRunnerXPLA3CPLDS系XCR3512XL-7-PQ208,速度为-7,综合后报告分析如下
图3为CPLD综合报告:
从报告中可以知道一共使用了87个MCs,占总体的17%,使用了208个PTs,占总体的14%,选这个型号似乎有点大材小用啊,不过资源很足够,满足设计的需求。
图4为CPLD时间报告:
由图4可知,时钟的最小周期为8.6ns,受clocktosetup影响最大,故关键路径为tcyc。
延时为8.6ns,时钟的工作频率为116.279MHz。
图3
图4
(3)ForFPGAimplementation(placeandroute)oftheFIFOs,howmanyLBs(logicblocks)?
Whichparameteriscriticaltothemaximuminternalclockworkingfrequency?
Trytofindoutthiscriticalparameteranditscorrespondingcircuitpath.
设置芯片为更换芯片型号为Spartan3-xc3s200-5pq208,速度为-5,其综合报告如下
图5为FPGA综合报告:
图5
图6为Spartan3datasheet
图6
图7
由上图知,对于选择的器件,其logiccell为4320,CLB有24X20=480个,每个CLB包含4个slice,而对于我们的程序,一共使用了66个slice,占总数的百分之三(总slice共计1920个),故使用的CLB数为66/4=16.5,即使用了17个。
由图7可知,时钟的最小周期为5.078ns,受clocktosetup影响最大,时钟的工作频率为196.927MHz。
(4)Trytosynthesizeagainthedesignwithtimingconstraintsandcomparewithitsformercounterparts.Youwillcreatethetimingconstraintyourselfandaddittoyourproject.PleaserefertothefollowinggraphicinterfaceofISE:
图8为timingconstrain设置图;
图9为没有设置时序约束时的报告;
图10为设置CLK周期约束为5ns时的报告;
图11为设置CLK周期约束为4.5ns时的报告;
图12设置clk周期约束为4ns时的报告
图13设置clk周期约束为3.5ns时的报告
图8
图9
图10
图11
图12
图13
3.FortheVHDLmodelgivenbelow(CodeListTwo),theremaybesomedesignerrorsinit.Somewarning(s)and/orerror(s)informationmaybeissuedwhensynthesizingit.Trytofindoutsuchdesignerrorsandcorrectthem.
仿真后无错误,有两个警告如下图:
图14
(1)程序中,输入端口rd没有使用到,其作用被oe所取代,因此可以将rd信号去掉,用oe来表示其功能,且不影响整个系统的设计。
(2)程序中输入信号端口en也未被使用,因为直接在fifo(wrptr)中取得了写地址的值,因此信号en也应去掉。
(3)语句dmuxout<=fifo(wrptr);应改为dmuxout<=fifo(rdptr);因为这时是读寄存器里的值,应该由读地址指针rdptr来指定应该读取哪个寄存器的值。
改进后加入激励得到图15的输出波形。
图15
8X9FIFOBUFFERDESIGNEXAMPLES
1#VHDLCODELIST:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityfifo89is
Port(clk:
instd_logic;
rst:
instd_logic;
rd:
instd_logic;
wr:
instd_logic;
rdinc:
instd_logic;
wrinc:
instd_logic;
rdptrclr:
instd_logic;
wrptrclr:
instd_logic;
data_in:
instd_logic_vector(8downto0);
data_out:
outstd_logic_vector(8downto0));
endfifo89;
--clk:
usedtosynchronizethebuffers;
--rst:
resetthebuffers
--rd:
whenvalid,theoutputbuffersareenabled;
--wr:
whenvalid,writeregisterwith9-bitwidthispermitted;
--rdinc:
readcounterenabled;
--wrinc:
writecounterenabled;
--rdptrclr:
resetreadcounter,pointingtothefirstregisterfor
--readpurpose;
--wrptrclr:
resetwritecounter,pointingtothefirstregisterfor
--writepurpose;
--data_in:
datainputswith9-bitwidthtotheFIFOs;
--data_out:
dataoutputswith9-bitwidthfromtheFIFOs.
architectureBehavioraloffifo89is
typefifo_arrayisarray(7downto0)ofstd_logic_vector(8downto0);
signalfifo:
fifo_array;
signalwrptr,rdptr:
std_logic_vector(2downto0);
signalen:
std_logic_vector(7downto0);
signaldmuxout:
std_logic_vector(8downto0);
begin
--fiforegister_array:
reg_array:
process(rst,clk)
begin
ifrst='1'then
foriin7downto0loop
fifo(i)<=(others=>'0');--aggregate
endloop;
elsif(clk'eventandclk='1')then
ifwr='1'then
foriin7downto0loop
ifen(i)='1'then
fifo(i)<=data_in;
else
fifo(i)<=fifo(i);
endif;
endloop;
endif;
endif;
endprocess;
--readpointer
read_count:
process(rst,clk)
begin
ifrst='1'then
rdptr<=(others=>'0');
elsif(clk'eventandclk='1')then
ifrdptrclr='1'then
rdptr<=(others=>'0');
elsifrdinc='1'then
rdptr<=rdptr+1;
endif;
endif;
endprocess;
--writepointer
write_count:
process(rst,clk)
begin
ifrst='1'then
wrptr<=(others=>'0');
elsif(clk'eventandclk='1')then
ifwrptrclr='1'then
wrptr<=(others=>'0');
elsifwrinc='1'then
wrptr<=wrptr+1;
endif;
endif;
endprocess;
--8:
1outputdatamux
withrdptrselect
dmuxout<=fifo(0)when"000",
fifo
(1)when"001",
fifo
(2)when"010",
fifo(3)when"011",
fifo(4)when"100",
fifo(5)when"101",
fifo(6)when"110",
fifo(7)whenothers;
--FIFOregisterselectordecoder
withwrptrselect
en<="00000001"when"000",
"00000010"when"001",
"00000100"when"010",
"00001000"when"011",
"00010000"when"100",
"00100000"when"101",
"01000000"when"110",
"10000000"whenothers;
--three-statecontrolofoutputs
three_state:
process(rd,dmuxout)
begin
ifrd='1'then
data_out<=dmuxout;
else
data_out<=(others=>'Z');
endif;
endprocess;
endBehavioral;
2#VHDLCODELIST:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityfifoxyisgeneric(wide:
integer:
=8);--widthis8+1
Port(clk:
instd_logic;
rst:
instd_logic;
oe:
instd_logic;
rd:
instd_logic;
wr:
instd_logic;
rdinc:
instd_logic;
wrinc:
instd_logic;
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