高速数字混合锁相环频率合成器大学毕业论文外文文献翻译及原文.docx

高速数字混合锁相环频率合成器大学毕业论文外文文献翻译及原文.docx

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高速数字混合锁相环频率合成器大学毕业论文外文文献翻译及原文

毕业设计（论文）

外文文献翻译

文献、资料中文题目：

高速数字混合锁相环频率合成器

文献、资料英文题目：

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专业：

通信工程

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姓名：

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翻译日期：

2017.02.14

锁相技术译文翻译

英文原名：

HighSpeedDigitalHybridPLLFrequencySynthesizer

译文：

高速数字混合锁相环频率合成器

英文

中文

HighSpeedDigitalHybridPLLFrequencySynthesizer

Abstract：

TheconventionalPLL（Phaselockedloop）frequencysynthesizertakesalongswitchingtimebecauseoftheinherentclosed-loopstructure.

ThedigitalhybridPLL（DH-PLL）whichincludestheopenloopstructureintotheconventionalPLLsynthesizerhasbeenstudiedtoovercomethisproblem.

Itoperatesinhighspeed,butthehardwarecomplexityandpowerconsumptionareotherseriousproblemssincetheDLT（digitallook-uptable）isusuallyimplementedbytheROMwhichcontainsthetransfercharacteristicofVCO（voltagecontrolledoscillator）.

ThispaperproposesanewDH-PLLusingaverysimpleDLT-replacementdigitallogicinsteadofthecomplexROM-typeDLT.

Also,atimingsynchronizationcircuitmakesthenegligibleovershootandmuchshortersettlingtimefortheultrafastswitchingspeed.

Also,thehardwarecomplexityandpowerconsumptiongetdecreasedtoabout28%,comparedwiththeconventionalDH-PLL.

KeyWords:

PLL,DLT,Frequencysynthesis

I.INTRODUCTION

Highspeedfrequencysynthesisisveryimportantandiswidelyusedintheelectronicandcommunicationsystemapplications.

In1999,El-Elaproposedthatadditionalsignalwhichisasynchronizedsaw-toothwaveformfromtheD/AconverterisinjectedintotheVCOinputoftheconventionalPLLfrequencysynthesizerforthehighspeedoperation[1].

However,itneedstheoptimalslopeanddurationateveryfrequencysynthesis.

Togetthehigh-speed,itisnecessarytopreparetheprecisesynchronizationofthecomplicateddesign.

In2001,H.G.RyuproposedasimplifiedstructureoftheDDFS（directdigitalfrequencysynthesizer）-drivenPLLforthehighswitchingspeed[2].

However,thereisaproblemthatthespeedofthewholesystemislimitedbyPLL.

Y.FouzarproposedaPLLfrequencysynthesizerofdualloopconfigurationusingfrequency-to-voltageconverter（FVC）[3].

IthasafastswitchingspeedbythePD（phasedetector）,FVCusingoutputsignalofVCOandtheproposedcoarsetuningcontroller.

However,H/Wcomplexityisincreasedforthehighswitchingspeed.

Also,itshowsthefastswitchingcharacteristiconlywhentheFVCworkswell.

Anothermethodispre-tuningonewhichiscalledDH-PLLinthisstudy[4].

Ithasveryhighspeedswitchingproperty,butH/Wcomplexityandpowerconsumptionareincreasedduetodigitallook-uptable（DLT）whichisusuallyimplementedbytheROMincludingthetransfercharacteristicofVCO（voltagecontrolledoscillator）.

Forthisreason,thispaperproposesatimingsynchronizationcircuitfortherapidfrequencysynthesisandaverysimpleDLTreplacementdigitallogicblockinsteadofthecomplexROMtypeDLTforhighspeedswitchingandlowpowerconsumption.

Also,therequisiteconditionissolvedintheproposedmethod.Thefastswitchingoperationateverythefrequencysynthesisprocessisverifiedbythecomputercircuitsimulation.

II.DH-PLLsynthesizer

AsshowninFig.1,theopen-loopsynthesizerisadirectfrequencysynthesistypethatVCOgeneratesthedesiredoutputbytheFCW（frequencycontrolword）inputfromtheD/Aconverter.

ThedigitalfrequencywordwhichisproducedfromtheROMtypeDLT（digitallook-uptable）containingtheVCOtransfercharacteristicgoesintoD/AconverterthatgeneratestheDCvaluecorrespondingtothedesiredVCOfrequency.

Fig.1.Open-loopfrequencysynthesizer.

TheDCvalueisalreadyfoundbythevoltage-frequencycharacteristicsofVCO.

Thisopen-loopfrequencysynthesizerhasfastswitchingspeed.

However,ithasthebigproblemsofstabilityandsensitivityduetotheinherentpropertiesoftheopenloopstructure.

Therefore,thissynthesizertypeisnotsoattractivethatthissynthesizerisnotwidelyused.

Fig.2.Closed-loopPLLfrequencysynthesizer.

InFig.2,FCW（frequencycontrolword）isthedivisionratiocommandforfrequencysynthesis.

Thisstructureisverypopularandexcellentintheaspectsofthestability,varietyandflexibility.

Also,thespuriousnoiseissmallerthanotherfrequencysynthesizer.

Ittakesthelongeracquisitiontimetojumpintoanewfrequencysothattheswitchingspeedislow.

Theswitchingtimegetslongerasthegenerationfrequencyspacingisincreased.

DH-PLLfrequencysynthesizerisshowninFig.3.

Fig.3.DH-PLLusingDLT（digitallook-uptable）.

Theopen-loopstructureoftheDLTandDACiscombinedintotheconventionalPLLclosed-loopstructure.

IntheconventionalPLL,theoutputvoltageofLFisfedtotheVCO.

Onthecontrary,sumofDACoutputvoltageandtheLFoutputvoltagedrivestheVCOwheneverFCWischanged.

Therefore,unlikeconventionalPLL,DACoutputsthesteadystatedrivingvoltageateverynewFCWchangetimessothathighspeedfrequencyswitchingmaybepossible.

However,theDH-PLLhasaseriousproblemofthephasechangeateverynewfrequencysynthesis.

AsshowninFig.4,theovershootandthesettlingtimehaveatrade-offrelationshipbecausetheoutputofprogrammabledividermovesintootherpointafterthenewFCWstart,eventhoughsystemparametersarepreviouslyoptimized.

So,ithasalongsettlingtimeandtheswitchingspeedgetsdown.

Phasedetectorinputsare②，③waveformsofFig.4whichareusedforthecontrolvoltageofLF（loopfilter）.

Therefore,therelationshipbetween②and③isfixeduntilanewFCWismade.

Fig.4.OperatingsignalofDH-PLL.

However,ifanewFCWistriggered,②waveformgoesdownthelow-state（"0"）inunexpectedplace,whichmeansavoltagechangestartofLF.

ThoughthereisasteadystatevoltagefromtheDAC,theovershoothappensforanewfrequencysynthesissothatsettlingprocesstakesalongtime.

LiketheconventionalPLL,theovershootandsettlingtimegetgreatlychangedforthewiderfrequencysynthesisspacing.

Inordertoovercomethisproblem,anewtimingsynchronizationcircuitisadditionallydesignedandthewholeDH-PLLstructureisshowninFig.5.

Fig.5.BlockdiagramofthenewproposedDH-PLL.

IV.Simulationresultsanddiscussion

Inthispaper,parametersoftable1andprocedureoftable2areusedtoverifytheswitchingfunctionoftheproposedDH-PLLcircuitstructure.

FCWisthedivisionratio.Fig.9and10aretheresultsofthecomputercircuitsimulations.

Divisionratiois8bitbinaryvalueandFCWchangesinevery1[msec].

ChangeofthedivisionratioshouldbemadeinthelinearregionofVCOtransfercurve.

InFig.10,theupperwaveformisinputdrivingvoltageofVCO,andthelowerisoutputvoltageofDAC.

AsshowninFig.10,thereareverysmallovershootandveryshortsettlingtimeinthefrequencysynthesistransitionprocessbecausetheinputtothephasedetectorissynchronizedwiththereferenceinputsignalirrespectiveofhowmanytheprogrammabledividercountstheVCOoutput.

OutputvoltageofDACis0[V]attheinitialstate.

Consequently,voltagefromDACandloopfilteroutputareaddedtodrivetheVCOsothatthedesiredfrequencymaybeobtained.

ItcanbeeasilyshownthattheinputdrivingvoltageofVCOisdifferentfromtheconventionalPLLclosed-loopstructureattheswitchingtimes.

ItisswiftlychangedbyoutputvoltageofDACandmovedintothesteadystatedrivingvoltageinaveryshortertimewheneverFCWvaries.

Fromtheseresults,itisshownthatDHPLLhasveryhighspeedswitchingfunction.

Also,wecancomparetheproposedDLT-replacementblockwiththeconventionalROMtypeDLTintheaspectsofthecircuitcomplexity.

V.Conclusion

Inthispaper,aDH-PLLsynthesizerusingsimpledigitallogiccircuitinsteadofROMtypeDLTblockisproposedtoovercomethecircuitcomplexityandpowerconsumptionoftheconventionalDH-PLL.

Infact,DLTblockisaburdenofhardwarecomplexityandtakesalongaccesstimetospeeddowntheswitchingoperation.

Inaddition,thereisanecessaryconditionthatthefirstfrequencycontrolwordshouldbesameattheinitialoperation.So,theproposedstructuresolvestherequisiteconditionandisverifiedbycomputersimulation.

Thehardwarecomplexityandpowerconsumptiongetsdecreasedtoabout28%,ascomparedwiththeconventionalDH-PLL.

FrequencysynthesizeroftheproposedDH-PLLstructurecanbeusedforthefastfrequencyhoppingsystem,electronicandcommunicationsystems.

REFERENCES

[1]El-Ela,M.A."HighspeedPLLfrequencysynthesizerwithsynchronousfrequencysweep,"NRSC'99.ProceedingsoftheSixteenthNational,pp.23-25,Feb.1999.

[2]H.G.Ryu,Y.Y.Kim,H.M.YuandS.B.Ryu,“DesignofDDFS-drivenPLLFrequencySynthesizerwithReducedComplexity,”IEEETransactionsonConsumerElectronics,Vol.47,No.1,Feb.2001.

[3]Fouzar,Y.,Sawan,M.,Savaria,Y."AnewfullyintegratedCMOSphase-lockedloopwithlowjitterandfastlocktime,"ISCAS2000Geneva.The2000IEEEInternationalSymposiumonCircuitsandSystems,Vol.2,pp.253-256,May2000.

[4]DavidM.Materna,“ALightweightFastHoppingSynthesizerForEHFSatelliteApplications,”MilitaryCommunicationsConference,MILCOM95,ConferenceRecord,IEEE,Vol.2,pp752-759,1995.

高速数字混合锁相环频率合成器

摘要：

传统的锁相环频率合成器需要很长的切换时间,因为其内在的闭环结构。

目前已经研发的一种数字混合锁相环来解决这一问题——在传统的锁相环频率合成器中加入开环结构。

它可以高速运行，但硬件复杂度和功耗是一个严重的问题，因为它的数字查找表（包含压控振荡器的传输特性）在ROM中频繁执行。

本文提出一种新的数字混合锁相环——使用一种简单的数字查找表代替复杂的ROM型数字查找表。

此外，定时同步电路使得环路超调量很小且建立时间短，从而保证了超高速切换速度。

同时,硬件复杂度和功耗比传统的数字混合锁相环（DH-PLL）大约降低28%。

关键词：

锁相环（PLL），数值查找表（DLT），频率合成

1简介

高速频率合成是一种非常重要的技术,被广泛地应用在电子和通信系统应用。

在19