交通灯信号控制器的设计实验报告.docx

交通灯信号控制器的设计实验报告.docx

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交通灯信号控制器的设计实验报告

交通灯信号控制器的设计

1、实验目的

（1）学习QuartusII软件的基本使用方法。

（2）学习VHDL程序的基本结构和基本语句。

2、实验内容

欲设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器，具体要求如下：

（1）主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。

（2）主干道处于常允许通行状态，支干道有车来时才允许通行；当主干道允许通行亮绿灯时，支干道亮红灯；支干道允许通行亮绿灯时，主干道亮红灯。

（3）当主、支道均有车时，两者交替允许通行，主干道每次放行45s，支干道每次放行25s，在每次由亮绿灯变成亮红灯的转换过程中，要亮5s的黄灯作为过渡，并进行减计时显示。

3、设计思路

交通控制器拟由单片的CPLD/FPGA来实现，经分析设计要求，整个系统由8个单元电路组成，包括：

JTDKZ：

交通灯状态控制

CNT45S：

45秒计时

CNT05S：

5秒计时

CNT25S：

25秒计时

XSKZ：

产生数码管段码数据，数据为BCD码

YMQ：

译码器，将BCD码转为段码

CTRLS：

产生数码管动态扫描信号

MUXB41：

4选1数据选择器，并产生位选信号

整个控制系统中，U1为交通灯控制模块JTDKZ，此模块根据主、支道传感器信号SM、SB以及来自时基发生电路的时钟信号CLK，发出主、支道指示灯的控制信号，同时向各定时单元、显示控制单元发出使能控制信号EN45、EN25、EN05M、EN05B;U2、U3、U4为45s、5s、25s定时单元CNT45S、CNT05S、CNT25S，这些单元根据SM、SB、CLK及JTDKZ发出的有关使能控制信号EN45、EN25、EN05M、EN05B，按要求进行定时，并将其输出传送至显示控制单元；U5为显示控制单元XSKZ，此单元根据JTDKZ发出的有关使能控制信号EN1、EN2、EN3、EN4选择定时单元CNT45S、CNT05S、CNT25S的输出，并将之传送至各显示译码器：

U6、U7、U8、U9为译码器YMQ，它将显示控制单元XSKZ的输出作为输入进行译码，将XSKZ的时间BCD码译码为数码管的8位段码，并将产生的段码经MUXB41送给数码管进行动态扫描显示的过程，动态扫描的选测信号由CTRLS产生。

在定时单元CNT45S和CNT25S的设计中，根据设计要求需要进行减计数，但本设计中仍使用的是加法计数，只是在将计数结果转换成两位BCD码时，将计数的最小值对应转换成显示定时的最大值，计数值加1时，转换的显示值减1，以此类推。

同时，由于主、支道从亮绿灯转到亮红灯中间有5s亮黄灯的时间过渡，因此对应的支、主道亮红灯的时间比对应的主、支道亮绿灯的时间要多5s，考虑到此原因，CNT45S和CNT25S计数器在把计数结果转换成显示的BCD码值时，将用于驱动绿灯的BCD码按实际定时要求转换，而将对应的用于驱动红灯的BCD码在实际定时要求的基础上加5进行转换。

4、实验设计

1）

系统原理框图

本系统总体可分为两个两个层次，即LED显示和数码管显示，核心模块为JTDKZ产生系统的所有信号

2）VHDL程序

◆JTDKZ的VHDL程序

--Jtdkz.vhd

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYJTDKZIS

PORT（CLK,SM,SB:

INSTD_LOGIC;

MR,MY,MG,BR,BY,BG:

OUTSTD_LOGIC）;

ENDENTITYJTDKZ;

ARCHITECTUREARTOFJTDKZIS

TYPESTATE_TYPEIS（A,B,C,D）;

SIGNALSTATE:

STATE_TYPE:

=A;

BEGIN

CNT:

PROCESS（CLK）IS

VARIABLES:

INTEGERRANGE0TO45:

=0;

VARIABLECLR:

BIT:

='0';

VARIABLEEN:

BIT:

='0';

BEGIN

IF（CLK'EVENTANDCLK='1'）THEN

IFCLR='0'THENS:

=0;

ELSIFEN='0'THENS:

=S;

ELSES:

=S+1;

ENDIF;

CASESTATEIS

WHENA=>MR<='0';MY<='0';MG<='1';BR<='1';BY<='0';BG<='0';

IF（SBANDSM）='1'THEN

IFS=45THENSTATE<=B;CLR:

='0';EN:

='0';

ELSESTATE<=A;CLR:

='1';EN:

='1';

ENDIF;

ELSIF（SBAND（NOTSM））='1'THEN

STATE<=C;CLR:

='0';EN:

='0';--STATE<=B

ELSESTATE<=A;CLR:

='1';EN:

='0';--

ENDIF;

WHENB=>MR<='0';MY<='1';MG<='0';BR<='1';BY<='0';BG<='0';

IFS=5THENSTATE<=C;CLR:

='0';EN:

='0';

ELSESTATE<=B;CLR:

='1';EN:

='1';

ENDIF;

WHENC=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='0';BG<='1';

IF（SBANDSM）='1'THEN

IFS=25THENSTATE<=D;CLR:

='0';EN:

='0';

ELSESTATE<=C;CLR:

='1';EN:

='1';

ENDIF;

ELSIFSB='0'THENSTATE<=A;CLR:

='0';EN:

='0';

ELSIFS=25THENSTATE<=D;CLR:

='0';EN:

='0';

ELSESTATE<=C;CLR:

='1';EN:

='1';

ENDIF;

WHEND=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='1';BG<='0';

IFS=5THENSTATE<=A;CLR:

='0';EN:

='0';

ELSESTATE<=D;CLR:

='1';EN:

='1';

ENDIF;

WHENOTHERS=>STATE<=A;

ENDCASE;

ENDIF;

ENDPROCESSCNT;

ENDARCHITECTUREART;

◆XSKZ的VHDL程序

--Xskz.vhd

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYXSKZIS

PORT（EN45,EN25,EN05M,EN05B:

INSTD_LOGIC;

AIN45M,AIN45B,AIN25M,AIN25B,AIN05:

INSTD_LOGIC_VECTOR（7DOWNTO0）;

DOUTM,DOUTB:

OUTSTD_LOGIC_VECTOR（7DOWNTO0））;

ENDENTITYXSKZ;

ARCHITECTUREARTOFXSKZIS

BEGIN

PROCESS（EN45,EN25,EN05M,EN05B,AIN45M,AIN45B,AIN25M,AIN25B,AIN05）IS

BEGIN

IFEN45='1'THENDOUTM<=AIN45M（7DOWNTO0）;DOUTB<=AIN45B（7DOWNTO0）;

ELSIFEN05M='1'THENDOUTM<=AIN05（7DOWNTO0）;DOUTB<=AIN05（7DOWNTO0）;

ELSIFEN25='1'THENDOUTM<=AIN25M（7DOWNTO0）;DOUTB<=AIN25B（7DOWNTO0）;

ELSIFEN05B='1'THENDOUTM<=AIN05（7DOWNTO0）;DOUTB<=AIN05（7DOWNTO0）;

ENDIF;

ENDPROCESS;

ENDARCHITECTUREART;

◆CNT05S的VHDL程序

--Cnt05s.vhd

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYCNT05SIS

PORT（CLK,EN05M,EN05B:

INSTD_LOGIC;

DOUT5:

OUTSTD_LOGIC_VECTOR（7DOWNTO0））;

ENDENTITYCNT05S;

ARCHITECTUREARTOFCNT05SIS

SIGNALCNT3B:

STD_LOGIC_VECTOR（2DOWNTO0）;

BEGIN

PROCESS（CLK,EN05M,EN05B）IS

BEGIN

IF（CLK'EVENTANDCLK='1'）THEN

IFEN05M='1'THENCNT3B<=CNT3B+1;

ELSIFEN05B='1'THENCNT3B<=CNT3B+1;

ELSIFEN05B='0'THENCNT3B<=CNT3B-CNT3B-1;

ENDIF;

ENDIF;

ENDPROCESS;

PROCESS（CNT3B）IS

BEGIN

CASECNT3BIS

WHEN"000"=>DOUT5<="00000101";

WHEN"001"=>DOUT5<="00000100";

WHEN"010"=>DOUT5<="00000011";

WHEN"011"=>DOUT5<="00000010";

WHEN"100"=>DOUT5<="00000001";

WHENOTHERS=>DOUT5<="00000000";

ENDCASE;

ENDPROCESS;

ENDARCHITECTUREART;

◆CNT25S的VHDL程序

--Cnt25s.vhd

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYCNT25SIS

PORT（SB,SM,CLK,EN25:

INSTD_LOGIC;

DOUT25M,DOUT25B:

OUTSTD_LOGIC_VECTOR（7DOWNTO0））;

ENDENTITYCNT25S;

ARCHITECTUREARTOFCNT25SIS

SIGNALCNT5B:

STD_LOGIC_VECTOR（4DOWNTO0）;

BEGIN

PROCESS（SB,SM,CLK,EN25）IS

BEGIN

IF（SB='0'ORSM='0'）THENCNT5B<=CNT5B-CNT5B-1;

ELSIF（CLK'EVENTANDCLK='1'）THEN

IFEN25='1'THENCNT5B<=CNT5B+1;

ELSIFEN25='0'THENCNT5B<=CNT5B-CNT5B-1;

ENDIF;

ENDIF;

ENDPROCESS;

PROCESS（CNT5B）IS

BEGIN

CASECNT5BISWHEN"00000"=>DOUT25M<="00100101";DOUT25B<="00110000";WHEN"00001"=>DOUT25M<="00100100";DOUT25B<="00101001";

WHEN"00010"=>DOUT25M<="00100011";DOUT25B<="00101000";

WHEN"00011"=>DOUT25M<="00100010";DOUT25B<="00100111";

WHEN"00100"=>DOUT25M<="00100001";DOUT25B<="00100110";WHEN"00101"=>DOUT25M<="00100000";DOUT25B<="00100101";

WHEN"00110"=>DOUT25M<="00011001";DOUT25B<="00100100";

WHEN"00111"=>DOUT25M<="00011000";DOUT25B<="00100011";

WHEN"01000"=>DOUT25M<="00010111";DOUT25B<="00100010";

WHEN"01001"=>DOUT25M<="00010110";DOUT25B<="00100001";

WHEN"01010"=>DOUT25M<="00010101";DOUT25B<="00100000";

WHEN"01011"=>DOUT25M<="00010100";DOUT25B<="00011001";

WHEN"01100"=>DOUT25M<="00010011";DOUT25B<="00011000";

WHEN"01101"=>DOUT25M<="00010010";DOUT25B<="00010111";

WHEN"01110"=>DOUT25M<="00010001";DOUT25B<="00010110";

WHEN"01111"=>DOUT25M<="00010000";DOUT25B<="00010101";

WHEN"10000"=>DOUT25M<="00001001";DOUT25B<="00010100";

WHEN"10001"=>DOUT25M<="00001000";DOUT25B<="00010011";

WHEN"10010"=>DOUT25M<="00000111";DOUT25B<="00010010";

WHEN"10011"=>DOUT25M<="00000110";DOUT25B<="00010001";

WHEN"10100"=>DOUT25M<="00000101";DOUT25B<="00010000";

WHEN"10101"=>DOUT25M<="00000100";DOUT25B<="00001001";

WHEN"10110"=>DOUT25M<="00000011";DOUT25B<="00001000";

WHEN"10111"=>DOUT25M<="00000010";DOUT25B<="00000111";

WHEN"11000"=>DOUT25M<="00000001";DOUT25B<="00000110";

WHENOTHERS=>DOUT25M<="00000000";DOUT25B<="00000000";

ENDCASE;

ENDPROCESS;

ENDARCHITECTUREART;

◆CNT45S的VHDL程序

--Cnt45s.vhd

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYCNT45SIS

PORT（SB,SM,CLK,EN45:

INSTD_LOGIC;

DOUT45M,DOUT45B:

OUTSTD_LOGIC_VECTOR（7DOWNTO0））;

ENDENTITYCNT45S;

ARCHITECTUREARTOFCNT45SIS

SIGNALCNT6B:

STD_LOGIC_VECTOR（5DOWNTO0）;

BEGIN

PROCESS（SB,SM,CLK,EN45）IS

BEGIN

IFSB='0'ORSM='0'THENCNT6B<=CNT6B-CNT6B-1;

ELSIF（CLK'EVENTANDCLK='1'）THEN

IFEN45='1'THENCNT6B<=CNT6B+1;

ELSIFEN45='0'THENCNT6B<=CNT6B-CNT6B-1;

ENDIF;

ENDIF;

ENDPROCESS;

PROCESS（CNT6B）IS

BEGIN

CASECNT6BIS

WHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000";

WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001";

WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000";

WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111";

WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110";

WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101";

WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100";

WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011";

WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010";

WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001";

WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000";

WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="00111001";

WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000";

WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111";

WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110";

WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101";

WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100";

WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011";

WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";

WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";

WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";

WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";

WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";

WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";

WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";

WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";

WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";

WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";

WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";

WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";

WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";

WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";

WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";

WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";

WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";

WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";

WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";

WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";

WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";

WHEN"101000"=>DOUT45M<="00000101";DOUT45B<="00010000";

WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";

WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";

WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";

WHEN"101100"=>