CPU报告.docx

CPU报告.docx

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CPU报告

ComputerOrganizationandArchitectureCourseDesign

CPUREPORT

04006628邓睿

04006618肖游龙

Time:

2009.04.08

Purpose

ThepurposeofthisprojectistodesignasimpleCPU（CentralProcessingUnit）.ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedconsiderthefollowingitems:

Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.

AtleastfourpartsconstituteasimpleCPU:

thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.

InstructionSet

Single-addressinstructionformatisusedinoursimpleCPUdesign.Theinstructionwordcontainstwosections:

theoperationcode（opcode）,whichdefinesthefunctionofinstructions（addition,subtraction,logicoperations,etc.）;theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.

Forsimplicity,thesizeofmemoryis256

16inthecomputer.Theinstructionwordhas16bits.Theopcodeparthas8bitsandaddressparthas8bits.TheinstructionwordformatcanbeexpressedinFigure4

Figure4theinstructionformat

InternalRegistersandMemory

MAR（MemoryAddressRegister）

MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.

MBR（MemoryBufferRegister）

MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.

PC（ProgramCounter）

PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.

IR（InstructionRegister）

IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.

BR（BufferRegister）

BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.

ACC（Accumulator）

ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.

MR（MultiplierRegister）

MRisusedforimplementingtheMPYinstruction,holdingthemultiplieratthebeginningoftheinstruction.Whentheinstructionisexecuted,itholdspartoftheproduct.

DR（DivisionRegister）

DRisusedforimplementingtheDIVinstruction,youcandefineitaccordingtoyourdivisionalgorithm.

LPM_RAM_DQ

LPM_RAM_DQisaRAMwithseparateinputandoutputports,itworksasmemory,anditssizeis256

16.Althoughit’snotaninternalregisterofCPU,weneedittosimulateandtesttheperformanceofCPU.

Alltheregistersarepositive-edge-triggered.

Alltheresetsignalsfortheregistersaresynchronizedtotheclocksignal.

ALU

ALU（ArithmeticLogicUnit）isacalculationunitwhichaccomplishesbasicarithmeticandlogicoperations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows

Table3ALUOperations

Operations

Explanations

ADD

（ACC）

（ACC）

（BR）

SUB

（ACC）

（ACC）

（BR）

AND

（ACC）

（ACC）and（BR）

OR

（ACC）

（ACC）or（BR）

NOT

（ACC）

Not（ACC）

SRL

（ACC）

Shift（ACC）toLeft1bit

SRR

（ACC）

Shift（ACC）toRight1bit

MicroprogrammedControlUnit

WehavelearnttheknowledgeofMicroprogrammedcontrolunit.Here,weonlyreviewsometermsandbasicstructures.

IntheMicroprogrammedcontrol,themicroprogramconsistsofsomemicroinstructionsandthemicroprogramisstoredincontrolmemorythatgeneratesallthecontrolsignalsrequiredtoexecutetheinstructionsetcorrectly.Themicroinstructioncontainssomemicro-operationswhichareexecutedatthesametime.

Figure5ControlUnitMicro-architecture

Figure5showsthekeyelementsofsuchanimplementation.Thesetofmicroinstructionsisstoredinthecontrolmemory.Thecontroladdressregistercontainstheaddressofthenextmicroinstructionstoberead.Whenamicroinstructionisreadfromthecontrolmemory,itistransferredtoacontrolbufferregister.Theregisterconnectstothecontrollinesemanatingfromthecontrolunit.Thus,readingamicroinstructionfromthecontrolmemoryisthesameasexecutingthatmicroinstruction.Thethirdelementshowninthefigureisasequencingunitthatloadsthecontroladdressregisterandissuesareadcommand.

CPUDesign

Figure6CPUdatapathandcontrolsignals

Figure6indicatesasimpleCPUarchitectureanditsuseofavarietyofinternaldatapathsandcontrolsignals.OurCPUdesignshouldbebasedonthisarchitecture.

Example:

LOADinstruction

Figure7ControlFlowchartoftheLOADinstruction

Table4SomeControlsignalsfortheLOADinstruction

BitinControlMemory

Micro-operation

Meaning

C0

CAR<=CAR+1

ControlAddressIncrement

C1

CAR<=***

ControlAddressRedirection,dependsonthepositionofmicroinstruction

C2

CAR<=0

ResetControlAddresstozeroposition

C3

MBR<=memory

MemoryContenttoMBR

C4

IR<=MBR[15..8]

CopyMBR[15..8]toIRforOPCODE

C5

MAR<=MBR[7..0]

CopyMBR[7..0]toMARforaddress

C6

PC<=PC+1

IncrementPCforindicatingposition

C7

BR<=MBR

CopyMBRdatatoBRforbuffertoALU

C8

ACC<=0

ResetACCregistertozero

C9

ACC<=ACC+BR

AddBRtoACC

C10

MAR<=PC

CopyPCvaluetoMARfornextaddress

…

……

……

Thenaccordingtothecontrolflowchartandthetable,themicroprogramandcontrolsignalsoftheLOADinstructionis:

Table5MicroprogramforLOADinstruction

Microprogram

Controlsignals

MBR<=memory,CAR<=CAR+1

C3,C0

IR<=MBR[15..8],CAR<=CAR+1

C4,C0

CAR<=***（***isdeterminedbyOPCODE）

C1

MAR<=MBR[7..0],PC<=PC+1,CAR<=CAR+1

C5,C6,C0

MBR<=memory,CAR<=CAR+1

C3,C0

BR<=MBR,ACC<=0,CAR<=CAR+1

C7,C8,C0

ACC<=ACC+BR,CAR<=CAR+1

C9,C0

MAR<=PC,CAR<=0

C10,C2

Designdescriptionresults

Accordingtotheintroductionanrequirements,wedesignedthemicrooperationsasfollows:

STOREX

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←ACC,CAR←CAR+1

memory←MBR,CAR←CAR+1W

MAR←PC7-0,CAR←0

C15,C4，

C17,C4

C5

C13,C19,C4

C16,C4

C14,C4

C12,C6

LOADX

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,ACC←0,CAR←CAR+1

ACC←ACC+BR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C24,C4

C22,C4

C12,C6

ADDX

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,CAR←CAR+1

ACC←ACC+BR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C22,C4

C12,C6

SUBX

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,CAR←CAR+1

ACC←ACC-BR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C23,C4

C12,C6

JMPGEZX

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

IFACC≥0THENPC←MBR9-0,CAR←CAR+1

MAR←PC,CAR←0

ELSEPC←PC+1,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C18,C4

C12,C6

C19,C4

C12,C6

HALT

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

PC←0,ACC←0,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C20,C24,C4

C12,C6

MPY

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

QR←MBR,CAR←CAR+1

MBR←ACC,CAR←CAR+1

BR←MBR,CAR←CAR+1

0←ACC,CNT←16,CAR←CAR+1

IFmulti_add=1thenACC←ACC+BR,SHIFTR

ELSIFmulti_sub=1thenACC←ACC-BR,SHIFTR

ELSIFmulti_shift=1thenSHIFTR

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C26,C4

C16,C4

C21,C4

C28,C26,C4

C27,C25,C22

C27,C25,C23

C27,C25

C12,C6

AND

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,CAR←CAR+1

ACC←ACCandBR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C1,C4

C12,C6

OR

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,CAR←CAR+1

ACC←ACCorBR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C2,C4

C12,C6

NOT

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,CAR←CAR+1

ACC←ACCnotBR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C3,C4

C12,C6

SHIFTR

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,ACC←0,CAR←CAR+1

ACC←ACC+BR,CAR←CAR+1

SHIFTRACC,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C24,C4

C22,C4

C25,C4

C12,C6

SHIFTL

MBR←memory,CAR←CAR+1R

IRopcode←MBR,CAR←CAR+1

（CAR←opcode）

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1R

BR←MBR,ACC←0,CAR←CAR+1

ACC←ACC+BR,CAR←CAR+1

SHIFTRACC,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C24,C4

C22,C4

C7,C4

C12,C6

Themeaningofeverybitofthecontrolmemory（ROM）accordingtoyourdesign.

Themicro-instructionsarestoredinthecontrolmemorysequentially,startingfrom00000000（HEX）.IfacontrolsignalisC12,the12thbitinthecontrolmemoryshouldbe1andtheothersareall0.

Bitinread-onlycontrolmemory（BitofROM）

Micro-operation

Controlsignalname

C12

MAR←PC7-0

PC_into_MA

C13

MAR←MBR7-0

MB_into_MA

C14

memo