VHDL程序题.docx
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VHDL程序题.docx
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VHDL程序题
1.以下是一位全加器的VHDL设计,试补充完整。
libraryieee;--半加器设计
use
entityh_adderis
port(a,b:
instd_logic;
co,so:
outstd_logic);
endh_adder;
architecturefh1ofh_adderis
begin
so<=not(axor(notb));
co<=aandb;
endarchitecturefh1;
libraryieee;--或门设计
useor2ais
port(a,b:
instd_logic;
c:
outstd_logic);
endor2a;
architecturertlofor2ais
begin
c<=aorbafter10ns;
endrt;
libraryieee;--全加器设计
useentityf_adderIS
port(ain,bin,cin:
instd_logic;
cout,sum:
outstd_logic);
endentityf_adder;
architecturefd1OFf_adderIS
componenth_adder
port(a,b:
instd_logic;
co,so:
outstd_logic);
endcomponent;
componentor2a
port(a,b:
instd_logic;
c:
outstd_logic);
endcomponent;
signald,e,f:
std_logic;
begin
u1:
h_adderportmap(a=>ain,b=>bin,co=>d,so=>e);
u2:
h_adderportmap(a=>e,b=>cin,co=>f,so=>sum);
u3:
or2aportmap(a=>d,b=>f,c=>cout);
endarchitecturefd1;
2.以下是含有使能端且具有同步清零的加减计数器的VHDL设计,试补充完整。
libraryieee;
usecounteris
port(updown,enable,clear,clk:
instd_logic;
q:
outintegerrange0to255);
endcounter;
architectureaofcounteris
begin
process(clk)
variablecnt:
integerrange0to(7);
variabledirection:
(8);
begin
if(updown='1')then
direction:
=1;
else
(9)
endif;
if(clk'eventandclk='1')then
ifclear='0'then
cnt:
=0;
else
ifenable='1'then
(10)
endif;
endif;
endif;
q<=cnt;
endprocess;
enda;
(7)255(8)integer(9)direction:
=-1;(10)cnt:
=cnt+direction
1.以下是8位分频器程序设计
LIBRARYIEEE;
USEPULSEIS
PORT(CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
FOUT:
OUTSTD_LOGIC);
END;
ARCHITECTUREoneOFPULSEIS
SIGNALFULL:
STD_LOGIC;
BEGIN
P_REG:
PROCESS(CLK)
VARIABLECNT8:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
IFCLK’EVENTANDCLK=‘1’THEN
IFCNT8=""THEN
CNT8:
=D;
FULL<='1';
ELSECNT8:
=CNT8+1;
FULL<='0';
ENDIF;
ENDIF;
ENDPROCESSP_REG;
P_DIV:
PROCESS(FULL)
VARIABLECNT2:
STD_LOGIC;
BEGIN
IFFULL'EVENTANDFULL='1'THEN
CNT2<=NOTCNT2;
IFCNT2='1'THENFOUT<='1';
ELSEFOUT<='0';
ENDIF;
ENDIF;
ENDPROCESSP_DIV;
END;
1.根据如下原理图,将相应VHDL描述补充完整。
Libraryieee;
Useprojis
Port(ain,bin,clk:
instd_logic;
Cout:
(1)std_logic);
Endproj;
Architectureoneof
(2)is
Signalt1,t2:
(3);
begin
(4)
Process(clk)begin
Ifclk’eventandclk=‘1’then
t1<=bin;
endif;
Endprocess;
Process((5))begin
If(6)thencout<=t2;endif;
Endprocess;
Endone;
2.用元件例化语句设计如图3-1所示电路。
LIBRARYieee;--底层2输入与非门
USEnand2IS
PORT(A1,B1:
INstd_logic;
C1:
OUTstd_logic));
ENDnand2;
ARCHITECTUREa1OFnand2IS
BEGIN
C1<=A1NANDB1;
ENDa1;
LIBRARYieee;--顶层设计
USEyf4IS
PORT(A,B,C,D:
INstd_logic;
Z:
OUTstd_logic));
ENDyf4;
ARCHITECTUREaOFyf4IS
COMPONENTnand2
PORT(A1,B1:
INstd_logic;
C1:
OUTstd_logic));
ENDCOMPONENT;
SIGNALX,Y:
std_logic;
BEGIN
U1:
nand2PORTMAP(A,B,X);
U2:
nand2PORTMAP(C,D,Y);
U3:
nand2PORTMAP(X,Y,Z);
ENDa;
1.根据如图3-1所示原理图将相应的VHDL程序补充完整。
Libraryieee;
Useyuanlituis
Port(A,B,clk:
instd_logic;
Qout:
outstd_logic);
Endyuanltu;
Architecturebehaveyuanlituis
Signals1,s2,s3:
std_logic;
Begin
s3<=s1nands2;
Process(clk)
Begin
Ifclk’eventandclk=‘1’then
s1<=A;
s2<=B;
Endif;
Endprocess;
Process(clk,s3)
Begin
Ifclk=‘1’then
Qout<=s3;
Endif;
Endprocess;
Endbehave;
1.以下VHDL程序实现
和
。
其中有两处错误,指出错误位置并改正。
01libraryieee;
02useuseentitytforis
05port(clk:
instd_logic;
06data:
inintegerrange0to1000000;
07ma,mb:
outintegerrange0to1000000);
08endtfor;
09architectureaoftforis
10begin
11process(clk,data)
12variablem1,m2:
integerrange0to1000000;
13begin
14m1:
=0;
15m2:
=0;
16ifclk='1'then
17foriindata'rangeloop
18ifi>=datathen
20exit;
21else
22m1:
=i+m1;
23m2:
=i+m2;
24endif;
25endloop;
26ma<=m1;mb<=m2;
27endif;
28endprocess;
29enda;
18行,改为ifi>datathen
23行,改为m2:
=i*i+m2;
1.8位二进制数判奇电路中有三处错误,指出错误位置并改正。
01LIBRARYIEEE;
02USE
03ENTITYp_checkIS
04PORT(a:
INSTD_LOGIC_VECTOR(7DOWNTO0);
05y:
OUTSTD_LOGIC);
06ENDp_check;
07ARCHITECTUREabcOFp_checkIS
08BEGIN
09PROCESS(a)
10VARIABLEtmp:
INTEGER;
11VARIABLEn:
INTEGER;
12BEGIN
13tmp:
='0';
14FORnin0TO7LOOP
15tmp:
=tmpXNORa(n);
16ENDLOOP;
17y<=tmp;
18ENDPROCESS;
19ENDabc;
10行,改为VARIABLEtmp:
STD_LOGIC;
11行,去掉
15行,改为tmp:
=tmpXORa(n);
2.以下是时钟设计中模24计数器的VHDL设计,试补充完整。
其中有两处错误,指出错误位置并改正。
01libraryieee;
02useuseentitycnt24is
05port(clk,clr:
instd_logic;
06ten,one:
outstd_logic_vector(3downto0);
07co:
outstd_logic);
08end;
09architectureoneofcnt24is
10signalten_temp,one_temp:
std_logic;
11begin
12process(clk,clr)
13begin
14ifclr='0'then
15ten_temp<="0000";
16one_temp<="0000";
17elsifclk'eventandclk='1'then
18iften_temp=2andone_temp=3then
19ten_temp<="0000";
20one_temp<="0000";
21elsifone_temp=9then
22one_temp<="0000";
23ten_temp<=ten_temp+1;
24elseone_temp<=one_temp+1;
25endif;
26endif;
27endprocess;
28ten<=ten_temp;
29one<=one_temp;
30co<='1'whenten_temp=2andone_temp=4else'0';
31end;
10行,改为signalten_temp,one_temp:
std_logic_vector(3downto0);
30行,改为co<='1'whenten_temp=2andone_temp=3else'0';
2.已知一个简单的波形发生器的数字部分系统框图如下图所示:
图中DOWNCNT、MYROM都是在QuartusII中使用MegaWizard调用的LPM模块,其VHDL描述中Entity部分分别如下:
ENTITYDOWNCNTIS
PORT(clock:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR(5DOWNTO0));
ENDDOWNCNT;
ENTITYmyromIS
PORT(address:
INSTD_LOGIC_VECTOR(5DOWNTO0);
Q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDmyrom;
该系统的顶层VHDL设计如下,其中有两处错误,指出错误位置并改正。
01Libraryieee;
02UseEntitymysgis
04Port(clk:
instd_logic;
05To_da:
outstd_logic_vector(7downto0));
06Endmysq;
07Architectureoneofmysqis
08Signaladdr:
std_logic_vector(5downto0);
09ComponentDOWNCNT
10Port(clock:
instd_logic;
11Q:
outstd_logic_vector(5downto0));
12Endcomponent;
13Component
14Port(address:
instd_logic_vector(5downto0);
15Q:
outstd_logic_vector(7downto0));
16Endcomponent;
17Begin
18U1:
DOWNCNTportmap(clock=>clk,q=>addr);
19U2:
myromportmap(addr=>address,q=>to_da);
20Endone;
13行,改为Componentmyrom
19行,改为U2:
myromportmap(address=>addr,q=>to_da);
--分频系数为5、占空比为1:
1的奇数分频器
libraryieee;
usediv5is
port
(clk:
instd_logic;
div5:
outstd_logic);
endentity;
architecturertlofdiv5is
signalcnt1:
std_logic_vector(2downto0);
signalcnt2:
std_logic_vector(2downto0);
signalclk_temp1:
std_logic;
signalclk_temp2:
std_logic;
constantm1:
integer:
=4;--计数器控制端1,m1=N-1
constantm2:
integer:
=2;--计数器控制端2,m2=(N-1)/2
begin
process(clk)--上升沿触发计数器进程
begin
ifclk'eventandclk='1'then
ifcnt1=m1then
cnt1<="000";
else
cnt1<=cnt1+1;
endif;
endif;
endprocess;
process(clk)--下降沿触发计数器进程
begin
ifclk'eventandclk='0'then
ifcnt2=m1then
cnt2<="000";
else
cnt2<=cnt2+1;
endif;
endif;
endprocess;
process(clk)--上升沿触发计数器的计数控制进程
begin
ifclk'eventandclk='1'then
ifcnt1=0then
clk_temp1<='1';
elsifcnt1=m2then
clk_temp1<='0';
endif;
endif;
endprocess;
process(clk)--下降沿触发计数器的计数控制进程
begin
ifclk'eventandclk='0'then
ifcnt2=0then
clk_temp2<='1';
elsifcnt2=m2then
clk_temp2<='0';
endif;
endif;
endprocess;
div5<=clk_temp1orclk_temp2;--将两个计数器控制的信号采用或逻辑
endrtl;
--占空比不是1:
1的偶数分频器,分频系数为6、占空比为1:
5的分频器
libraryieee;
usediv6is
port(clk:
instd_logic;
div6:
outstd_logic);
endentity;
architecturertlofdiv6is
signalcnt:
std_logic_vector(2downto0);
signalclk_temp:
std_logic;
constantm:
integer:
=5;--控制计数器的常量,m=N-1
begin
process(clk)
begin
if(rising_edge(clk))then
ifcnt=mthen
clk_temp<='1';
cnt<="000";
else
cnt<=cnt+1;
clk_temp<='0';
endif;
endif;
endprocess;
div6<=clk_temp;
endrtl;
--分频系数为7、占空比为1:
6的奇数分频器
libraryieee;
usediv7is
port(clk:
instd_logic;
div7:
outstd_logic);
endentity;
architecturertlofdiv7is
signalcnt:
std_logic_vector(2downto0);
signalclk_temp:
std_logic;
constantm:
integer:
=6;--控制计数器的常量,m=N-1
begin
process(clk)
begin
if(rising_edge(clk))then
ifcnt=mthen
clk_temp<='1';
cnt<="000";
else
cnt<=cnt+1;
clk_temp<='0';
endif;
endif;
endprocess;
div7<=clk_temp;
endrtl;
--分频系数不是2的整数次幂的分频器
libraryieee;
usediv12is
port(clk:
instd_logic;
div12:
outstd_logic);
endentity;
architecturertlofdiv12is
signalcnt:
std_logic_vector(2downto0);
signalclk_temp:
std_logic;
constantm:
integer:
=5;--控制计数器的常量,m=(N/2)-1
begin
process(clk)
begin
if(rising_edge(clk))then
ifcnt=mthen
clk_temp<=notclk_temp;--计数器值与m相等时clk_temp翻转
cnt<="000";
else
cnt<=cnt+1;
endif;
endif;
endprocess;
div12<=clk_temp;
endrtl;
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