EDA数字钟设计.docx
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EDA数字钟设计.docx
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EDA数字钟设计
EDA数字钟设计
数字钟
--EDA课程设计
姓名:
专业:
班级:
指导教师:
一、数字钟的设计要求
(1)具有正确的时、分、秒计时功能。
(2)计时结果要用6个数码管分别显示时、分、秒的十位和个位。
(3)有校时功能。
当键MINUTE按下时,分计数器以秒脉冲的速度递增,并按60min循环,即计数到59min后再回00。
当HOUR键按下时,时计数器以秒脉冲的速度递增,并按24h循环,即计数到23h后再回00。
二、数字钟顶层结构
根据数字钟的功能要求,就可以对数字钟按照功能进行模块划分。
图2-1是它的顶层电路原理图。
在图2-1中,外界通过CLK端输入1Hz的脉冲信号。
1Hz信号作为秒脉冲信号送入SECOND(60进制)计数器进行秒计时,满60s产生一个进位信号CARRY,经过或门被送入MINUTE(60进制)计数器进行分计数。
当按下SECOND键后,1Hz秒脉冲信号通过或门被送入MINUTE(60进制)计数器进行分计数,从而实现快速校分功能。
HOUR(24进制)计数器也是经过同样的过程实现计数和校时功能。
时、分、秒计数器的输出均是十位和个位分开显示的8421BCD码,将这六组BCD码通过一个六选一数据选择器MUX6_1SCAN选出一组BCD码。
由外界输入的CLKCAN信号作为MUX6_1SCAN的选择控制信号,然后再将选出的一组BCD码送至七段译码显示器进行译码。
译码每输出结果同时送至6个LED数码管的a、b、c、d、e、f7个段,至于哪个数码管能够显示,取决于扫描控制信号SEL的输出结果,即SEL选择哪个数码管,那个数码管就点亮。
用多个(6个)数码管显示数据时有并行显示和动态扫描显示两种方式。
所谓并行显示,是6个数码管同时被驱动,它需要同时对6组BCD码数据进行编译,并输出6组LED7段驱动信号去驱动6个数码管的7个显示段,共需要42个I/O管脚,另外还需要6个BCD/7段译码器。
本设计采用动态扫描显示,每次仅仅点亮1个数码管,各个数码管轮流被扫描点亮,如果扫描的速度足够快,由于人眼存在视觉暂留现象,就看不出闪烁。
开始工作时,先从6组BCD数据中选出一组,通过7段译码器译码后输出,然后选出下一组数据译码输出。
数据选择的时序和顺序由6个进制计数器SEL控制,与此同时,MUX6_1SCAN产生选通信号。
这种显示方式需要的资源少,而且节能。
。
图2-1数字钟的顶层原理图
三、数字钟各模块的VHDL源程序设计
以下是数字钟各模块的VHDL程序及部分主要模块的仿真波形。
整体模块VHDL代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYs_clock_signalIS
PORT(clk,reset:
INSTD_LOGIC;ca1,ca2,ca3:
outstd_logic;
seline:
outstd_logic_vector(2downto0);
seg7:
outstd_logic_vector(7downto0);
seg_s_l,seg_s_h,seg_m_l,seg_m_h,seg_h_l,seg_h_h:
bufferintegerrange0to9);
ENDENTITYs_clock_signal;
ARCHITECTUREmzmOFs_clock_signalIS
SIGNALsec1_t,sec2_t,min1_t,min2_t,hour1_t,hour2_t:
integerrange0to9;
SIGNALcarry1,carry2,carry3:
STD_LOGIC;
SIGNALcnt:
std_logic_vector(2downto0);
SIGNALcnt_freq:
integerrange0to999;
SIGNALsel:
std_logic_vector(2downto0);
SIGNALclk_1Hz:
std_logic;
functioni2seg7(i:
inintegerrange0to9)
returnstd_logic_vectoris
variableseg7:
std_logic_vector(7downto0);
begin
caseiis
when0=>
seg7:
=x"3f";--digitaltubesdisplay0to9
when1=>
seg7:
=x"06";
when2=>
seg7:
=x"5B";
when3=>
seg7:
=x"4F";
when4=>
seg7:
=x"66";
when5=>
seg7:
=x"6D";
when6=>
seg7:
=x"7D";
when7=>
seg7:
=x"07";
when8=>
seg7:
=x"7F";
when9=>
seg7:
=x"6F";
whenothers=>
seg7:
=(others=>'0');
endcase;
returnseg7;
endfunctioni2seg7;
BEGIN
p1:
PROCESS(clk_1Hz,reset,sec1_t,sec2_t)
BEGIN
IFreset='1'THEN
sec1_t<=0;
sec2_t<=0;
ELSIFrising_edge(clk_1Hz)THEN
IFsec1_t=9THEN
sec1_t<=0;
IFsec2_t=5THEN
sec2_t<=0;
ELSE
sec2_t<=sec2_t+1;
ENDIF;
ELSE
sec1_t<=sec1_t+1;
ENDIF;
IF(sec1_t=9ANDsec2_t=5)THEN
carry1<='1';
ELSE
carry1<='0';
ENDIF;
ENDIF;
seg_s_l<=sec1_t;
seg_s_h<=sec2_t;
ENDPROCESSp1;
p2:
PROCESS(reset,min1_t,min2_t,carry1)
BEGIN
IFreset='1'THEN
min1_t<=0;
min2_t<=0;
ELSIFrising_edge(carry1)THEN
IFmin1_t=9THEN
min1_t<=0;
IFmin2_t=5THEN
min2_t<=0;
ELSE
min2_t<=min2_t+1;
ENDIF;
ELSE
min1_t<=min1_t+1;
ENDIF;
IF(min1_t=9ANDmin2_t=5)THEN
carry2<='1';
ELSE
carry2<='0';
ENDIF;
ENDIF;
seg_m_l<=min1_t;
seg_m_h<=min2_t;
ENDPROCESSp2;
p3:
PROCESS(reset,hour1_t,hour2_t,carry2,carry3)
BEGIN
IFreset='1'THEN
hour1_t<=0;
hour2_t<=0;
ELSIFrising_edge(carry2)THEN
IF(hour1_t=3ANDhour2_t=2)THEN
hour1_t<=0;
hour2_t<=0;
ELSE
IFhour1_t=9THEN
hour1_t<=0;
IFhour2_t=2THEN
hour2_t<=0;
ELSE
hour2_t<=hour2_t+1;
ENDIF;
ELSE
hour1_t<=hour1_t+1;
ENDIF;
ENDIF;
IF(hour1_t=0ANDhour2_t=0)THEN
carry3<='1';
ELSE
carry3<='0';
ENDIF;
ENDIF;
seg_h_l<=hour1_t;
seg_h_h<=hour2_t;
ENDPROCESSp3;
ca1<=carry1;
ca2<=carry2;
ca3<=carry3;
p4:
process(clk,reset,sel)
begin
ifreset='1'then
cnt<=(others=>'0');
cnt_freq<=0;
clk_1Hz<='0';
elsifrising_edge(clk)then
ifcnt=7then--6countertoscandigitaltubes
cnt<=(others=>'0');
else
cnt<=cnt+1;
endif;
ifcnt_freq=999then--1kdivid
cnt_freq<=0;
clk_1Hz<=notclk_1Hz;
else
cnt_freq<=cnt_freq+1;
ifcnt_freq=499then
clk_1Hz<=notclk_1Hz;
endif;
endif;
casecntis--dynamicscaning
when"000"=>
sel<="000";
seg7<=i2seg7(seg_s_l);
when"001"=>
sel<="001";
seg7<=i2seg7(seg_s_h);
when"010"=>
sel<="010";
seg7<="01000000";
when"011"=>
sel<="011";
seg7<=i2seg7(seg_m_l);
when"100"=>
sel<="100";
seg7<=i2seg7(seg_m_h);
when"101"=>
sel<="101";
seg7<="01000000";
when"110"=>
sel<="110";
seg7<=i2seg7(seg_h_l);
when"111"=>
sel<="111";
seg7<=i2seg7(seg_h_h);
whenothers=>
sel<="ZZZ";
endcase;
seline<=sel+"001";
endif;
endprocessp4;
ENDmzm;
(1)秒计数器的源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYsecondIS
PORT(clk,reset:
INSTD_LOGIC;
sec1,sec2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
carry:
OUTSTD_LOGIC);
ENDsecond;
ARCHITECTURErt1OFsecondIS
SIGNALsec1_t,sec2_t:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,reset)
BEGIN
IFreset='1'THEN
sec1_t<="0000";
sec2_t<="0000";
ELSIFclk'eventANDclk='1'THEN
IFsec1_t="1001"THEN
sec1_t<="0000";
IFsec2_t="0101"THEN
sec2_t<="0000";
ELSE
sec2_t<=sec2_t+1;
ENDIF;
图3-1秒计数器
ELSE
sec1_t<=sec1_t+1;
ENDIF;
IFsec1_t="1001"AND
sec2_t="0101"THEN
carry<='1';
ELSE
carry<='0';
ENDIF;
ENDIF;
sec1<=sec1_t;
sec2<=sec2_t;
ENDPROCESS;
ENDrt1;
图3-2秒计数器仿真波形
图3-3秒计数器局部放大仿真波形
(2)分计数器的源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYminuteIS
PORT(clk,reset:
INSTD_LOGIC;
min1,min2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
carry:
OUTSTD_LOGIC);
ENDminute;
ARCHITECTURErt1OFminuteIS
SIGNALmin1_t,min2_t:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,reset)
BEGIN
IFreset='1'THEN
min1_t<="0000";
min2_t<="0000";
ELSIFclk'eventANDclk='1'THEN
IFmin1_t="1001"THEN
min1_t<="0000";
IFmin2_t="0101"THEN
min2_t<="0000";
ELSE
min2_t<=min2_t+1;
ENDIF;
ELSE
min1_t<=min1_t+1;
ENDIF;
图3-3分计数器
IFmin1_t="1001"AND
min2_t="0101"THEN
carry<='1';
ELSE
carry<='0';
ENDIF;
ENDIF;
min1<=min1_t;
min2<=min2_t;
ENDPROCESS;
ENDrt1;
图3-4分计数器仿真波形
图3-5分计数器局部放大仿真波形
(3)时计数器的源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYhourIS
PORT(clk,reset:
INSTD_LOGIC;
hour1,hour2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
carry:
OUTSTD_LOGIC);
ENDhour;
ARCHITECTURErt1OFhourIS
SIGNALhour1_t:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALhour2_t:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,reset)
BEGIN
IFreset='1'THEN
hour1_t<="0000";
hour2_t<="0000";
ELSIFclk'eventANDclk='1'THEN
IFhour1_t="0011"AND
hour2_t="0010"THEN
hour1_t<="0000";
hour2_t<="0000";
ELSE
IFhour1_t="1001"THEN
hour1_t<="0000";
IFhour2_t="0010"THEN
hour2_t<="0000";
ELSE
hour2_t<=hour2_t+1;
ENDIF;
ELSE
hour1_t<=hour1_t+1;
ENDIF;
ENDIF;
IFhour1_t="0000"AND
hour2_t="0000"THEN
图3-6时计数器
carry<='1';
ELSE
carry<='0';
ENDIF;
ENDIF;
hour1<=hour1_t;
hour2<=hour2_t;
ENDPROCESS;
ENDrt1;
(5)扫描源程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclock_dynamicis
port(
clk,rst:
instd_logic;--clk:
1KHz
--sel:
outstd_logic_vector(5downto0);
sel:
outstd_logic_vector(2downto0);
seg7:
outstd_logic_vector(7downto0)
);
endentityclock_dynamic;
architecturebehaviorofclock_dynamicis
signalclk_1Hz:
std_logic;
signalseg_s_l,seg_s_h,seg_m_l,seg_m_h,seg_h_l,seg_h_h:
integerrange0to9;
signalcnt:
std_logic_vector(2downto0);
signalcnt_freq:
integerrange0to999;
functioni2seg7(i:
inintegerrange0to9)
returnstd_logic_vectoris
variableseg7:
std_logic_vector(7downto0);
begin
caseiis
when0=>
seg7:
="10111111";
when1=>
seg7:
="10000110";
when2=>
seg7:
="11011011";
when3=>
seg7:
="11001111";
when4=>
seg7:
="11100110";
when5=>
seg7:
="11101101";
when6=>
seg7:
="11111101";
when7=>
seg7:
="10000111";
when8=>
seg7:
="11111111";
when9=>
seg7:
="11100111";
whenothers=>
seg7:
=(others=>'0');
endcase;
returnseg7;
endfunctioni2seg7;
components_clock_signalis
port(
rst:
instd_logic;--resettimeto00:
00:
00
clk:
instd_logic;--assume1Hz
seg_s_l:
outintegerrange0to9;
seg_s_h:
outintegerrange0to9;
seg_m_l:
outintegerrange0to9;
seg_m_h:
outintegerrange0to9;
seg_h_l:
outintegerrange0to9;
seg_h_h:
outintegerrange0to9
);
endcomponents_clock_signal;
begin
u1:
s_clock_signalportmap(
rst=>rst,
clk=>clk_1Hz,
seg_s_l=>seg_s_l,
seg_s_h=>seg_s_h,
seg_m_l=>seg_m_l,
seg_m_h=>seg_m_h,
seg_h_l=>seg_h_l,
seg_h_h=>seg_h_h
);
process(clk,rst)is
begin
ifrst='0'then
cnt<=(others=>'0');
cnt_freq<=0;
clk_1Hz<='0';
elsifrising_edge(clk)then
ifcnt=5then
cnt<=(others=>'0');
else
cnt<=cnt+1;
endif;
ifcnt_freq=999then
cnt_freq<=0;
clk_1Hz<=notclk_1Hz;
else
cnt_freq<=cnt_freq+1;
ifcnt_freq=499then
clk_1Hz<=notclk_1Hz;
endif;
endif;
casecntis
when"000"=>
--sel<="000001";
sel<="000";
seg7<=i2seg7(seg_s_l);
when"001"=>
--sel<="000010";
sel<="001";
seg7<=i2seg
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