TMS320C5402资料英文翻译.docx
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TMS320C5402资料英文翻译.docx
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TMS320C5402资料英文翻译
附件9:
本科毕业设计
外文文献及译文
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TMS320C5402
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信息与电气工程学院
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外文文献
TMS320C5402
AdvancedMultibusArchitectureWithThreeSeparate16-BitDataMemoryBusesandOneProgramMemoryBus.40-BitArithmeticLogicUnit(ALU),Includinga40-BitBarrelShifterandTwoIndependent40-BitAccumulators1717-BitParallelMultiplierCoupledtoa40-BitDedicatedAdderforNon-PipelinedSingle-CycleMultiply/Accumulate(MAC)Operation.Compare,Select,andStoreUnit(CSSU)fortheAdd/CompareSelectionoftheViterbiOperator.ExponentEncodertoComputeanExponentValueofa40-BitAccumulatorValueinaSingleCycle.TwoAddressGeneratorsWithEightAuxiliaryRegistersandTwoAuxiliaryRegisterArithmeticUnits(ARAUDataBusWithaBus-HolderFeature.ExtendedAddressingModefor1M16-Bit
MaximumAddressableExternalProgramSpace.4Kx16-BitOn-ChipROM.16Kx16-BitDual-AccessOn-ChipRAM.Single-Instruction-RepeatandBlock-RepeatOperationsforProgramCode.Block-Memory-MoveInstructionsforEfficientProgramandDataManagement.InstructionsWitha32-BitLongWordOperand.InstructionsWithTwo-orThree-OperandReads.ArithmeticInstructionsWithParallelStoreandParallelLoad.ConditionalStoreInstructionsFastReturnFromInterruptOn-ChipPeripheralsSoftware-ProgrammableWait-StateGeneratorandProgrammableBankSwitchingOn-ChipPhase-LockedLoop(PLL)ClockGeneratorWithInternalOscillatororExternalClockSource.TwoMultichannelBufferedSerialPorts(McBSPs).Enhanced8-BitParallelHost-PortInterface(HPI8).Two16-BitTimers,Six-ChannelDirectMemoryAccess(DMA)Controller.PowerConsumptionControlWithIDLE1,IDLE2,andIDLE3InstructionsWithPower-DownModes.CLKOUTOffControltoDisableCLKOUTOn-ChipScan-BasedEmulationLogic,IEEEStd1149.1†(JTAG)BoundaryScanLogic10-nsSingle-CycleFixed-PointInstructionExecutionTime(100MIPS)for3.3-VPowerSupply(1.8-VCore).Availableina144-PinPlasticLow-ProfileQuadFlatpack(LQFP)(PGESuffix)anda144-PinBallGridArray(BGA)(GGUSuffix).
1.description
TheTMS320VC5402fixed-point,digitalsignalprocessor(DSP)(hereafterreferredtoasthe’5402unlessotherwisespecified)isbasedonanadvancedmodifiedHarvardarchitecturethathasoneprogrammemorybusandthreedatamemorybuses.Thisprocessorprovidesanarithmeticlogicunit(ALU)withahighdegreeofparallelism,application-specifichardwarelogic,on-chipmemory,andadditionalon-chipperipherals.ThebasisoftheoperationalflexibilityandspeedofthisDSPisahighlyspecializedinstructionset.
Separateprogramanddataspacesallowsimultaneousaccesstoprograminstructionsanddata,providingthehighdegreeofparallelism.Tworeadoperationsandonewriteoperationcanbeperformedinasinglecycle.Instructionswithparallelstoreandapplication-specificinstructionscanfullyutilizethisarchitecture.Inaddition,datacanbetransferredbetweendataandprogramspaces.Suchparallelismsupportsapowerfulsetofarithmetic,logic,andbit-manipulationoperationsthatcanbeperformedinasinglemachinecycle.Inaddition,the’5402includesthecontrolmechanismstomanageinterrupts,repeatedoperations,andfunctioncalls.
2.memory
The’5402deviceprovidesbothon-chipROMandRAMmemoriestoaidinsystemperformanceandintegration.
3.on-chipROMwithbootloader
The’5402featuresa4K-word16-biton-chipmaskableROM.CustomerscanarrangetohavetheROMofthe’5402programmedwithcontentsuniquetoanyparticularapplication.AsecurityoptionisavailabletoprotectacustomROM.ThissecurityoptionisdescribedintheTMS320C54xDSPCPUandPeripheralsReferenceSet,Volume1(literaturenumberSPRU131).NotethatonlytheROMsecurityoption,andnottheROM/RAMoption,isavailableonthe’5402.Abootloaderisavailableinthestandard’5402on-chipROM.Thisbootloadercanbeusedtoautomaticallytransferusercodefromanexternalsourcetoanywhereintheprogrammemoryatpowerup.IftheMP/MCpinissampledlowduringahardwarereset,executionbeginsatlocationFF80hoftheon-chipROM.Thislocationcontainsabranchinstructiontothestartofthebootloaderprogram.Thestandard’5402bootloaderprovidesdifferentwaystodownloadthecodetoaccomodatevarioussystemrequirements:
(1)Parallelfrom8-bitor16-bit-wideEPROM
(2)ParallelfromI/Ospace8-bitor16-bitmode
(3)Serialbootfromserialports8-bitor16-bitmode
(4)Host-portinterfaceboot
Thestandardon-chipROMlayoutisshown
4.on-chipRAM
The’5402devicecontains16K16-bitofon-chipdual-accessRAM(DARAM).TheDARAMiscomposedoftwoblocksof8Kwordseach.EachblockintheDARAMcansupporttworeadsinonecycle,orareadandawriteinonecycle.TheDARAMislocatedintheaddressrange0060h–3FFFhindataspace,andcanbemappedintoprogram/dataspacebysettingtheOVLYbittoone.
5.relocatableinterruptvectortable
Thereset,interrupt,andtrapvectorsareaddressedinprogramspace.Thesevectorsaresoft—meaningthattheprocessor,whentakingthetrap,loadstheprogramcounter(PC)withthetrapaddressandexecutesthecodeatthevectorlocation.Fourwordsarereservedateachvectorlocationtoaccommodateadelayedbranchinstruction,eithertwo1-wordinstructionsorone2-wordinstruction,whichallowsbranchingtotheappropriateinterruptserviceroutinewithminimaloverhead.Atdevicereset,thereset,interrupt,andtrapvectorsaremappedtoaddressFF80hinprogramspace.However,thesevectorscanberemappedtothebeginningofany128-wordpageinprogramspaceafterdevicereset.Thisisdonebyloadingtheinterruptvectorpointer(IPTR)bitsinthePMSTregister(seeFigure2)withtheappropriate128-wordpageboundaryaddress.AfterloadingIPTR,anyuserinterruptortrapvectorismappedtothenew128-wordpage.NOTE:
Thehardwarereset(RS)vectorcannotberemappedbecauseahardwareresetloadstheIPTRwith1s.Therefore,theresetvectorisalwaysfetchedatlocationFF80hinprogramspace.
6.ProcessorModeStatus(PMST)Registers
extendedprogrammemory
The’5402usesapagedextendedmemoryschemeinprogramspacetoallowaccessofupto1024Kprogrammemorylocations.Inordertoimplementthisscheme,the’5402includesseveralfeaturesthatarealsopresentonthe’548/’549devices:
Twentyaddresslines,insteadofsixteenAnextramemory-mappedregister,theXPCregister,definesthepageselection.Thisregisterismemory-mappedintodataspacetoaddress001Eh.Atahardwarereset,theXPCisinitializedto0.Sixextrainstructionsforaddressingextendedprogramspace.ThesesixinstructionsaffecttheXPC.FB[D]pmad(20bits)–Farbranch
FBACC[D]Accu[19:
0]–FarbranchtothelocationspecifiedbythevalueinaccumulatorAoraccumulatorBFCALL[D]pmad(20bits)–FarcallFCALA[D]Accu[19:
0]–FarcalltothelocationspecifiedbythevalueinaccumulatorAoraccumulatorBFRET[D]–FarreturnFRETE[D]–FarreturnwithinterruptsenabledInadditiontothesenewinstructions,two’54xinstructionsareextendedtouse20bitsinthe’5402:
READAdata_memory(using20-bitaccumulatoraddress).WRITAdata_memory(using20-bitaccumulatoraddress)Allotherinstructions,softwareinterruptsandhardwareinterruptsdonotmodifytheXPCregisterandaccessonlymemorywithinthecurrentpage.Programmemoryinthe’5402isorganizedinto16pagesthatareeach64Kinlength,asshowninFigure3.
7.on-chipperipherals
The’5402devicehasthefollowingperipherals:
Software-programmablewait-stategeneratorwithprogrammablebank-switchingwaitstates.
(1)Anenhanced8-bithost-portinterface(HPI8).
(2)Twomultichannelbufferedserialports(McBSPs).
(3)Twohardwaretimers.
(4)Aclockgeneratorwithaphase-lockedloop(PLL).
(5)Adirectmemoryaccess(DMA)controller.
8.software-programmablewait-stategenerator
Thesoftwarewait-stategeneratorofthe’5402canextendexternalbuscyclesbyuptofourteenmachinecycles.DevicesthatrequiremorethanfourteenwaitstatescanbeinterfacedusingthehardwareREADYline.Whenallexternalaccessesareconfiguredforzerowaitstates,theinternalclockstothewait-stategeneratorareautomaticallydisabled.Disablingthewait-stategeneratorclocksreducesthepowercomsumptionofthe’5402.
Thesoftwarewait-stateregister(SWWSR)controlstheoperationofthewait-stategenerator.The14LSBsoftheSWWSRspecifythenumberofwaitstates(0to7)tobeinsertedforexternalmemoryaccessestofiveseparateaddressranges.Thisallowsadifferentnumberofwaitstatesforeachofthefiveaddressranges.Additionally,thesoftwarewait-statemultiplier(SWSM)bitofthesoftwarewait-statecontrolregister(SWCR)definesamultiplicationfactorof1or2forthenumberofwaitstates.Atreset,thewait-stategeneratorisinitializedtoprovidesevenwaitstatesonallexternalmemoryaccesses.
9.parallelI/Oports
The’5402hasatotalof64KI/Oports.TheseportscanbeaddressedbythePORTRinstructionorthePORTWinstruction.TheISsignalindicatesaread/writeoperationthroughanI/Oport.The’5402caninterfaceeasilywithexternaldevicesthroughtheI/Oportswhilerequiringminimaloff-chipaddress-decodingcircuits.
10.enhanced8-bithost-portinterface
The’5402host-portinterface,alsoreferredtoastheHPI8,isanenhancedversionofthestandard8-bitHPIfoundonearlier’54xDSPs(’542,’545,’548,and’549).TheHPI8isan8-bitparallelportforinterprocessorcommunication.ThefeaturesoftheHPI8include:
Standardfeatures:
Sequentialtransfers(withautoincrement)orrandom-accesstransfers,Hostinterruptand’54xinterruptcapability,Multipledatastrobesandcontrolpinsforinterfa
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