EDA复习.docx
- 文档编号:4346332
- 上传时间:2022-11-30
- 格式:DOCX
- 页数:23
- 大小:20.61KB
EDA复习.docx
《EDA复习.docx》由会员分享,可在线阅读,更多相关《EDA复习.docx(23页珍藏版)》请在冰豆网上搜索。
EDA复习
EDA复习
4.1.12选1多路选择器的VHDL描述
【例4-1】
ENTITYmux21aIS
PORT(a,b:
INBIT;
s:
INBIT;
y:
OUTBIT);
ENDENTITYmux21a;
ARCHITECTUREoneOFmux21aIS
BEGIN
y<=aWHENs='0'ELSEb;
ENDARCHITECTUREone;
【例4-2】
ENTITYmux21a1IS
PORT(a,b:
INBIT;
s:
INBIT;
y:
OUTBIT);
ENDENTITYmux21a1;
ARCHITECTUREoneOFmux21a1IS
SIGNALd,e:
BIT;
BEGIN
d<=aAND(NOTS);
e<=bANDs;
y<=dORe;
ENDARCHITECTUREone;
【例4-3】
ENTITYmux21a2IS
PORT(a,b,s:
INBIT;
y:
OUTBIT);
ENDENTITYmux21a2;
ARCHITECTUREoneOFmux21a2IS
BEGIN
PROCESS(a,b,s)
BEGIN
IFs='0'THEN
y<=a;ELSE
y<=b;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREone;
4.2.1D触发器的VHDL描述
【例4-6】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDFF1IS
PORT(CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFDFF1IS
SIGNALQ1:
STD_LOGIC;--类似于在芯片内部定义一个数据的暂存节点
BEGIN
PROCESS(CLK,Q1)
BEGIN
IFCLK'EVENTANDCLK='1'
THENQ1<=D;
ENDIF;
ENDPROCESS;
Q<=Q1;--将内部的暂存数据向端口输出(双横线--是注释符号)
ENDbhv;
4.3.1半加器描述
【例4-16】
LIBRARYIEEE;--半加器描述
(1):
布尔方程描述方法
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_adderIS
PORT(a,b:
INSTD_LOGIC;
co,so:
OUTSTD_LOGIC);
ENDENTITYh_adder;
ARCHITECTUREfh1OFh_adderis
BEGIN
so<=NOT(aXOR(NOTb));co<=aANDb;
ENDARCHITECTUREfh1;
【例4-17】
LIBRARYIEEE;--半加器描述
(2):
真值表描述方法
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_adderIS
PORT(a,b:
INSTD_LOGIC;
co,so:
OUTSTD_LOGIC);
ENDENTITYh_adder;
ARCHITECTUREfh1OFh_adderis
SIGNALabc:
STD_LOGIC_VECTOR(1DOWNTO0);--定义标准逻辑位矢量数据类型
BEGIN
abc<=a&b;--a相并b,即a与b并置操作
PROCESS(abc)
BEGIN
CASEabcIS--类似于真值表的CASE语句
WHEN"00"=>so<='0';co<='0';
WHEN"01"=>so<='1';co<='0';
WHEN"10"=>so<='1';co<='0';
WHEN"11"=>so<='0';co<='1';
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREfh1;
【例4-18】
LIBRARYIEEE;--或门逻辑描述
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYor2aIS
PORT(a,b:
INSTD_LOGIC;
c:
OUTSTD_LOGIC);
ENDENTITYor2a;
ARCHITECTUREoneOFor2aIS
BEGIN
c<=aORb;
ENDARCHITECTUREone;
【例4-19】
LIBRARYIEEE;--1位二进制全加器顶层设计描述
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYf_adderIS
PORT(ain,bin,cin:
INSTD_LOGIC;
cout,sum:
OUTSTD_LOGIC);
ENDENTITYf_adder;
ARCHITECTUREfd1OFf_adderIS
COMPONENTh_adder--调用半加器声明语句
PORT(a,b:
INSTD_LOGIC;
co,so:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTor2a
PORT(a,b:
INSTD_LOGIC;
c:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALd,e,f:
STD_LOGIC;--定义3个信号作为内部的连接线。
BEGIN
u1:
h_adderPORTMAP(a=>ain,b=>bin,co=>d,so=>e);--例化语句
u2:
h_adderPORTMAP(a=>e,b=>cin,co=>f,so=>sum);
u3:
or2aPORTMAP(a=>d,b=>f,c=>cout);
ENDARCHITECTUREfd1;
4.4四进制计数器设计
【例4-20】
ENTITYCNT4IS
PORT(CLK:
INBIT;
Q:
BUFFERINTEGERRANGE15DOWNTO0);
END;
ARCHITECTUREbhvOFCNT4IS
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
Q<=Q+1;
ENDIF;
ENDPROCESS;
ENDbhv;
4.5一般加法计数器设计
【例4-22】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT10IS
PORT(CLK,RST,EN:
INSTD_LOGIC;
CQ:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
COUT:
OUTSTD_LOGIC);
ENDCNT10;
ARCHITECTUREbehavOFCNT10IS
BEGIN
PROCESS(CLK,RST,EN)
VARIABLECQI:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
IFRST=‘1’THENCQI:
=(OTHERS=>’0’);--计数器异步复位
ELSIFCLK’EVENTANDCLK=‘1’THEN--检测时钟上升沿
IFEN=‘1’THEN--检测是否允许计数(同步使能)
IFCQI<9THENCQI:
=CQI+1;--允许计数,检测是否小于9
ELSECQI:
=(OTHERS=>‘0’);--大于9,计数值清零
ENDIF;
ENDIF;
ENDIF;
IFCQI=9THENCOUT<=‘1’;--计数大于9,输出进位信号
ELSECOUT<=‘0’;
ENDIF;
CQ<=CQI;--将计数值向端口输出
ENDPROCESS;
ENDbehav;
4.5.3含并行置位的移位寄存器设计
【例4-23】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSHFRTIS--8位右移寄存器
PORT(CLK,LOAD:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(7DOWNTO0);
QB:
OUTSTD_LOGIC);
ENDSHFRT;
ARCHITECTUREbehavOFSHFRTIS
BEGIN
PROCESS(CLK,LOAD)
VARIABLEREG8:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFLOAD='1'THENREG8:
=DIN;--由(LOAD='1')装载新数据
ELSEREG8(6DOWNTO0):
=REG8(7DOWNTO1);
ENDIF;
ENDIF;
QB<=REG8(0);--输出最低位
ENDPROCESS;
ENDbehav;
6.1.4进程中的信号与变量赋值
【例6-1】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.all;
ENTITYDFF3IS
PORT(CLK,D1:
INSTD_LOGIC;
Q1:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFDFF3IS
BEGIN
PROCESS(CLK)
VARIABLEQQ:
STD_LOGIC;
BEGIN
IFCLK'EVENTANDCLK='1'THENQQ:
=D1;
ENDIF;
ENDPROCESS;
Q1<=QQ;
END;
【例6-2】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.all;
ENTITYDFF3IS
PORT(CLK,D1:
INSTD_LOGIC;
Q1:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFDFF3IS
SIGNALQQ:
STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THENQQ<=D1;
ENDIF;
ENDPROCESS;
Q1<=QQ;
END;
【例6-3】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDFF3IS
PORT(CLK,D1:
INSTD_LOGIC;
Q1:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFDFF3IS
SIGNALA,B:
STD_LOGIC;
BEGIN
PROCESS(CLK)BEGIN
IFCLK'EVENTANDCLK='1'THEN
A<=D1;
B<=A;
Q1<=B;
ENDIF;
ENDPROCESS;
END;
【例6-4】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDFF3IS
PORT(CLK,D1:
INSTD_LOGIC;
Q1:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFDFF3IS
BEGIN
PROCESS(CLK)
VARIABLEA,B:
STD_LOGIC;
BEGIN
IFCLK'EVENTANDCLK='1'THEN
A:
=D1;
B:
=A;
Q1<=B;
ENDIF;
ENDPROCESS;
END;
6.1.4进程中的信号与变量赋值
【例6-7】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(i0,i1,i2,i3,a,b:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREbody_mux4OFmux4IS
BEGIN
process(i0,i1,i2,i3,a,b)
variablemuxval:
integerrange7downto0;
begin
muxval:
=0;
if(a='1')thenmuxval:
=muxval+1;endif;
if(b='1')thenmuxval:
=muxval+2;endif;
casemuxvalis
when0=>q<=i0;
when1=>q<=i1;
when2=>q<=i2;
when3=>q<=i3;
whenothers=>null;
endcase;
endprocess;
ENDbody_mux4;
【例6-8】
LibraryIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSHIFTIS
PORT(CLK,C0:
INSTD_LOGIC;--时钟和进位输入
MD:
INSTD_LOGIC_VECTOR(2DOWNTO0);--移位模式控制字
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);--待加载移位的数据
QB:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);--移位数据输出
CN:
OUTSTD_LOGIC);--进位输出
ENDENTITY;
ARCHITECTUREBEHAVOFSHIFTIS
SIGNALREG:
STD_LOGIC_VECTOR(7DOWNTO0);
SIGNALCY:
STD_LOGIC;
BEGIN
PROCESS(CLK,MD,C0)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
CASEMDIS
WHEN"001"=>REG(0)<=C0;
REG(7DOWNTO1)<=REG(6DOWNTO0);CY<=REG(7);--带进位循环左移
WHEN“010”=>REG(0)<=REG(7);
REG(7DOWNTO1)<=REG(6DOWNTO0);--自循环左移
WHEN"011"=>REG(7)<=REG(0);
REG(6DOWNTO0)<=REG(7DOWNTO1);--自循环右移
WHEN"100"=>REG(7)<=C0;
REG(6DOWNTO0)<=REG(7DOWNTO1);CY<=REG(0);--带进位循环右移
WHEN"101"=>REG(7DOWNTO0)<=D(7DOWNTO0);--加载待移数
WHENOTHERS=>REG<=REG;CY<=CY;--保持
ENDCASE;
ENDIF;
ENDPROCESS;
QB(7DOWNTO0)<=REG(7DOWNTO0);CN<=CY;--移位后输出
ENDBEHAV;
6.2.1三态门设计
【例6-9】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYtri_sIS
port(enable:
INSTD_LOGIC;
datain:
INSTD_LOGIC_VECTOR(7DOWNTO0);
dataout:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDtri_s;
ARCHITECTUREbhvOFtri_sIS
BEGIN
PROCESS(enable,datain)
BEGIN
IFenable='1'THENdataout<=datain;
ELSEdataout<="ZZZZZZZZ";
ENDIF;
ENDPROCESS;
ENDbhv;
6.2.2双向端口设计
【例6-10】
libraryieee;
useieee.std_logic_1164.all;
entitytri_stateis
port(control:
instd_logic;
in1:
instd_logic_vector(7downto0);
q:
inoutstd_logic_vector(7downto0);
x:
outstd_logic_vector(7downto0));
endtri_state;
architecturebody_trioftri_stateis
begin
process(control,q,in1)
begin
if(control='0')thenx<=q;q<="ZZZZZZZZ";
elseq<=in1;x<="ZZZZZZZZ“;
endif;
endprocess;
endbody_tri;
6.2.3三态总线电路设计
【例6-12】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYtristate2IS
port(input3,input2,input1,input0:
INSTD_LOGIC_VECTOR(7DOWNTO0);
enable:
INSTD_LOGIC_VECTOR(1DOWNTO0);
output:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDtristate2;
ARCHITECTUREmultiple_driversOFtristate2IS
BEGIN
PROCESS(enable,input3,input2,input1,input0)
BEGIN
IFenable="00"THENoutput<=input3;
ELSEoutput<=(OTHERS=>'Z');
ENDIF;
IFenable="01"THENoutput<=input2;
ELSEoutput<=(OTHERS=>'Z');
ENDIF;
IFenable="10"THENoutput<=input1;
ELSEoutput<=(OTHERS=>'Z');
ENDIF;
IFenable="11"THENoutput<=input0;
ELSEoutput<=(OTHERS=>'Z');
ENDIF;
ENDPROCESS;
ENDmultiple_drivers;
数据溢出及其处理
解决方法—用并置符扩展位,但不能解决减法溢出的问题
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityarith_unsignedis
Port(a,b:
instd_logic_vector(3downto0);
s1,s2:
outstd_logic_vector(4downto0));
endarith_unsigned;
architectureoneofarith_unsignedis
begin
s1<=('0'&a)+('0'&b);
s2<=('0'&a)-('0'&b);
end;
减法溢出的解决方法—用并置符在数据前补符号位:
数据前用并置符补符号位后,既解决了加法溢出的问题,也解决了减法溢出的问题!
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityarith_signedis
Port(a,b:
instd_logic_vector(3downto0);
s1,s2:
outstd_logic_vector(4downto0));
endarith_signed;
architectureoneofarith_signedis
begin
s1<=(a(3)&a)+(b(3)&b);
s2<=(a(3)&a)-(b(3)&b);
end;
8.1.3一般有限状态机的设计
【例8-1】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYs_machineIS
PORT(clk,reset:
INSTD_LOGIC;
state_inputs:
INSTD_LOGIC_VECTOR(0TO1);
comb_outputs:
OUTINTEGERRANGE0TO15);
ENDs_machine;
ARCHITECTUREbehvOF
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA 复习