EDA实验报告 1.docx
- 文档编号:4336212
- 上传时间:2022-11-29
- 格式:DOCX
- 页数:15
- 大小:20.04KB
EDA实验报告 1.docx
《EDA实验报告 1.docx》由会员分享,可在线阅读,更多相关《EDA实验报告 1.docx(15页珍藏版)》请在冰豆网上搜索。
EDA实验报告1
汕头大学实验报告
学院:
工学院系:
电子系专业:
电子年级:
2009地点:
工西407
姓学号:
09141068合作者:
实验时间:
2012-4-21
实验二时序逻辑电路的VHDL模型实验
一、实验目的
1、了解普通4×4键盘扫描的原理。
2、掌握组合逻辑电路和时序逻辑电路的混和设计。
3、进一步加深七段码管显示过程的理解。
二、实验原理
本实验主要完成的实验是完成4×4键盘扫描的,然后获取其键值,并对其进行编码,从而进行按键的识别,并将相应的按键值进行显示。
键盘扫描的实现过程如下:
对于4×4键盘,通常连接为4行、4列,因此要识别按键,只需要知道是哪一行和哪一列即可,为了完成这一识别过程,我们的思想是,首先固定输出4行为高电平,然后输出4列为低电平,在读入输出的4行的值,通常高电平会被低电平拉低,如果读入的4行均为高电平,那么肯定没有按键按下,否则,如果读入的4行有一位为低电平,那么对应的该行肯定有一个按键按下,这样便可以获取到按键的行值。
同理,获取列值也是如此,先输出4列为高电平,然后在输出4行为低电平,再读入列值,如果其中有哪一位为低电平,那么肯定对应的那一列有按键按下。
获取到行值和列值以后,组合成一个8位的数据,根据实现不同的编码在对每个按键进行匹配,找到键值后在7段码管和LED显示。
三、实验内容及步骤
本实验内容是完成4×4键盘的扫描,然后将正确的键值进行显示,实验步骤如下:
1、编写键盘扫描和显示的VHDL代码。
2、用Quartus对其进行编译仿真。
3、在仿真确定无误后,选择芯片ACEX1KEP1K30QC208。
4、给芯片进行管脚绑定,在此进行编译。
5、根据自己绑定的管脚,在实验箱上对键盘接口、显示接口和FPGA之间进行正确连线。
6、给目标板下载代码,在4×4键盘输入键值,观看实验结果。
四、实验中主要仪器设备
1、4×4键盘阵列。
2、FPGA主芯片。
3、可变时钟源。
4、七段码显示区。
5、LED显示模块。
五、实验程序分析
4×4键盘的扫描VHDL代码:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityscanfis
port(clk:
instd_logic;-------------扫描时钟信号
start:
instd_logic;-------------开始信号,高电平有效
kbcol:
instd_logic_vector(3downto0);--------------行扫描信号
kbrow:
outstd_logic_vector(3downto0);-------------列扫描信号
seg7_out:
outstd_logic_vector(6downto0);-------------七段显示控制信号(abcdefg)
scan:
outstd_logic_vector(2downto0));-----------数码管地址选择控制信号
endscanf;
architectureoneofscanfis
signalcount:
std_logic_vector(1downto0);
signalsta:
std_logic_vector(1downto0);
signalseg7:
std_logic_vector(6downto0);
signaldat:
std_logic_vector(4downto0);
signalfn:
std_logic;------------------按键标志位,判断是否有键被按下
begin
scan<="000";---------------只使用一个数码管显示
---------------------循环扫描计数器
process(clk)
begin
ifclk'eventandclk='1'thencount<=count+1;
endif;
endprocess;
---------------------循环列扫描
process(clk)
begin
ifclk'eventandclk='1'then
casecountis
when"00"=>kbrow<="0001";sta<="00";
when"01"=>kbrow<="0010";sta<="01";
when"10"=>kbrow<="0100";sta<="10";
when"11"=>kbrow<="1000";sta<="11";
whenothers=>kbrow<="1111";
endcase;
endif;
endprocess;
---------------------行扫描译码
process(clk,start)
begin
ifstart='0'thenseg7<="0000000";
elsifclk'eventandclk='1'then
casestais
when"00"=>
casekbcolis
when"0001"=>seg7<="1111001";dat<="00011";-----3
when"0010"=>seg7<="1101101";dat<="00010";-----2
when"0100"=>seg7<="0110000";dat<="00001";-----1
when"1000"=>seg7<="1111110";dat<="00000";-----0
whenothers=>seg7<="0000000";dat<="11111";
endcase;
when"01"=>
casekbcolis
when"0001"=>seg7<="1110000";dat<="00111";-----7
when"0010"=>seg7<="1011111";dat<="00110";-----6
when"0100"=>seg7<="1011011";dat<="00101";-----5
when"1000"=>seg7<="0110011";dat<="00100";-----4
whenothers=>seg7<="0000000";dat<="11111";
endcase;
when"10"=>
casekbcolis
when"0001"=>seg7<="0011111";dat<="01011";-----b
when"0010"=>seg7<="1110111";dat<="01010";-----a
when"0100"=>seg7<="1111011";dat<="01001";-----9
when"1000"=>seg7<="1111111";dat<="01000";-----8
whenothers=>seg7<="0000000";dat<="11111";
endcase;
when"11"=>
casekbcolis
when"0001"=>seg7<="1000111";dat<="01111";-----f
when"0010"=>seg7<="1001111";dat<="01110";-----e
when"0100"=>seg7<="0111101";dat<="01101";-----d
when"1000"=>seg7<="1001110";dat<="01100";-----c
whenothers=>seg7<="0000000";dat<="11111";
endcase;
whenothers=>seg7<="0000000";
endcase;
endif;
endprocess;
fn<=not(dat(0)anddat
(1)anddat
(2)anddat(3)anddat(4));
-------------------产生按键标志位,用于存储按键信息
process(fn)
begin
iffn'eventandfn='1'then------------按键信息存储
seg7_out<=seg7;
endif;
endprocess;
endone;
从实验的结果可以看出,当使能端处于高电平即有效电平时,把时钟输出按键打开。
2、按键加1或减1显示并且移位VHDL代码:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityabc2is
port(
key1:
instd_logic;
key2:
instd_logic;
clk:
instd_logic;
wei:
outstd_logic_vector(2downto0);
led_seg:
outstd_logic_vector(7downto0);
out0:
outstd_logic_vector(2downto0);
out1:
outstd_logic_vector(2downto0);
out2:
outstd_logic_vector(2downto0);
out3:
outstd_logic_vector(2downto0);
out4:
outstd_logic_vector(2downto0);
out5:
outstd_logic_vector(2downto0));
end;
architectureaofabc2is
signaltemp1:
std_logic_vector(2downto0);
signaltemp2:
std_logic_vector(2downto0);
signalflag1:
std_logic_vector(1downto0);
signalflag2:
std_logic_vector(1downto0);
---signalwei_si:
std_logic_vector(2downto0);
signalnum:
std_logic_vector(2downto0);
signalnum0:
std_logic_vector(2downto0);
signalnum1:
std_logic_vector(2downto0);
signalnum2:
std_logic_vector(2downto0);
signalnum3:
std_logic_vector(2downto0);
signalnum4:
std_logic_vector(2downto0);
signalnum5:
std_logic_vector(2downto0);
signalnum6:
std_logic_vector(2downto0);
signalnum7:
std_logic_vector(2downto0);
begin
p1:
process(clk)
variablewei_si:
std_logic_vector(2downto0):
="000";
begin
ifclk'eventandclk='1'then
temp1(0)<=key1;
temp1
(1)<=temp1(0);
temp1
(2)<=temp1
(1);
temp2(0)<=key2;
temp2
(1)<=temp2(0);
temp2
(2)<=temp2
(1);
iftemp1="111"then
flag1(0)<='1';
flag1
(1)<=flag1(0);
endif;
iftemp1="000"then
flag1(0)<='0';
flag1
(1)<=flag1(0);
endif;
iftemp2="111"then
flag2(0)<='1';
flag2
(1)<=flag2(0);
endif;
iftemp2="000"then
flag2(0)<='0';
flag2
(1)<=flag2(0);
endif;
ifflag1="10"then
num0<=num0+1;
num1<=num0;
num2<=num1;
num3<=num2;
num4<=num3;
num5<=num4;
num6<=num5;
num7<=num6;
endif;
ifflag2="10"then
num0<=num0-1;
num1<=num0;
num2<=num1;
num3<=num2;
num4<=num3;
num5<=num4;
num6<=num5;
num7<=num6;
endif;
wei_si:
=wei_si+1;
wei<=wei_si;
casewei_siis
when"000"=>num<=num0;
when"001"=>num<=num1;
when"010"=>num<=num2;
when"011"=>num<=num3;
when"100"=>num<=num4;
when"101"=>num<=num5;
when"110"=>num<=num6;
when"111"=>num<=num7;
endcase;
endif;
endprocessp1;
--p3:
process(clk,wei_si)
--begin
---endprocessp3;
p4:
process(clk,num)
begin
casenumis
when"000"=>led_seg<="01000000";
when"001"=>led_seg<="01111001";
when"010"=>led_seg<="00100100";
when"011"=>led_seg<="00110000";
when"100"=>led_seg<="00011001";
when"101"=>led_seg<="00010010";
when"110"=>led_seg<="00000010";
when"111"=>led_seg<="01111000";
whenothers=>null;
endcase;
endprocessp4;
out0<=num;
out1<=num1;
out2<=num2;
out3<=num3;
out4<=num4;
out5<=num5;
end;
3、键盘扫描带有去抖并且移位
VHDL代码:
--按键
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjianpanis
port(
clk:
instd_logic;--100mhz==0.01us1us100
col:
instd_logic_vector(3downto0);
row:
outstd_logic_vector(3downto0);
wei:
outstd_logic_vector(2downto0);
duan:
outstd_logic_vector(7downto0)
);
end;
architectureaofjianpanis
signalcount:
std_logic_vector(16downto0);
signalwei_s:
std_logic_vector(2downto0);
signalt:
std_logic_vector(5downto0);
signalflag:
std_logic;
signalnum0:
std_logic_vector(4downto0);--integer;
signalnum1:
std_logic_vector(4downto0);--integer;
signalnum2:
std_logic_vector(4downto0);--integer;
signalnum3:
std_logic_vector(4downto0);--integer;
signalnum4:
std_logic_vector(4downto0);--integer;
signalnum5:
std_logic_vector(4downto0);--integer;
signalnum6:
std_logic_vector(4downto0);--integer;
signalnum7:
std_logic_vector(4downto0);--integer;
signalnum8:
std_logic_vector(4downto0);--integer;
signalduan_s:
std_logic_vector(4downto0);--integer;
signalold_num:
std_logic_vector(4downto0);--integer;
signalp_num:
std_logic_vector(4downto0);--integer;
signalstate:
std_logic_vector(4downto0);--integer;
begin
process(clk)
begin
ifclk'eventandclk='1'then
count<=count+1;
ifcount="11000011010100000"then
count<=(others=>'0');
endif;
endif;
endprocess;
process(clk,count(16))
begin
ifcount(16)'eventandcount(16)='0'then
--ifclk'eventandclk='1'then
wei_s<=wei_s+1;
t<=t+1;
endif;
endprocess;
wei<=wei_s;
process(wei_s)
begin
casewei_sis
when"000"=>duan_s<=num1;
when"001"=>duan_s<=num2;
when"010"=>duan_s<=num3;
when"011"=>duan_s<=num4;
when"100"=>duan_s<=num5;
when"101"=>duan_s<=num6;
when"110"=>duan_s<=num7;
when"111"=>duan_s<=num8;
--whenothers=>wei_s<="000";
endcase;
endprocess;
process(duan_s,clk)
begin
caseduan_sis
when"00000"=>duan<="01111110";
when"00001"=>duan<="00011000";
when"00010"=>duan<="01101101";
when"00011"=>duan<="00111101";
when"00100"=>duan<="00011011";
when"00101"=>duan<="00110111";
when"00110"=>duan<="01110111";
when"00111"=>duan<="00011100";
when"01000"=>duan<="01111111";
when"01001"=>duan<="00011111";
when"01010"=>duan<="01110111";
when"01011"=>duan<="00011111";
when"01100"=>duan<="01001110";
when"01101"=>duan<="00111101";
when"01110"=>duan<="01001111";
when"01111"=>duan<="01000111";
whenothers=>null;
endcase;
endprocess;
process(clk,state)
begin
casestateis
when"00000"=>row<="1110";
when"00001"=>row<="1101";
when"00010"=>row<="1011";
when"00011"=>row<="0111";
whenothers=>null;
endcase;
end
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA实验报告 EDA 实验 报告