东南大学计算结构POC报告.docx

东南大学计算结构POC报告.docx

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东南大学计算结构POC报告

ComputerOrganizationandArchitecture

COURSEDESIGN

NAME

STUDENTNUMBER

COURSE

ComputerOrganizationandArchitectureCourseDesign

PROJECT

AParallelOutputControllerBasingOnVerilogHDL

SOFTWAREPLATFORM

ISE14.1

DATE

MAR.17.2014

1.Purpose

（1）Todesignandsimulateaparalleloutputcontroller（POC）whichactsaninterfacebetweensystembusandprinter.

（2）TheuseofISEsoftwarefordesignandsimulation.

2.Tasks

（1）POCisoneofthemostcommonI/Omodules,namelytheparalleloutputcontroller.Itplaystheroleofaninterfacebetweenthecomputersystembusandtheperipheral（suchasaprinterorotheroutputdevices）.

Figure1PrinterConnection

FigureshowstheconnectingofaprintertothesystembusthroughthePOC.

（2）ThecommunicationbetweenPOCandtheprinteriscontrolledbya“handshake”protocolillustratedinFigure.

Figure2Thehandshake-timingdiagrambetweenPOCandtheprinter

Thehandshakingprocessisdescribedasfollows:

Whentheprinterisreadytoreceiveacharacter,itholdsRDY=1.ThePOCmustthenholdacharacteratPD（paralleldata）portandproduceapulseattheterminalTR（transferrequest）.TheprinterwillchangeRDYto0,takethecharacteratPDandholdtheRDYat0untilthecharacterhasbeenprinted（e.g.5or10ms）,thensetRDY=1againwhenitisreadytoreceivethenextcharacter.（Supposetheprinterhasonlyaonecharacter“buffer”register,sothateachcharactermustbeprintedbeforethenextcharacterissent）.

（3）ThebufferregisterBRisusedtoholdacharacterthathasbeensentviathesystembuswhilethatthecharacterisbeingtransferredtotheprinter.ThestatusregisterSRisusedfortwocontrolfunctions:

SR7servesasareadyflagforsystembustransferstoBR（liketheprinterRDYsignalfortransfersfromPOCtotheprinter）,andSR0isusedtoenableordisableinterruptrequestsfromPOC.IfSR0=1,thenPOCwillinterruptwhenitisreadytoreceiveacharacter（i.e.,whenSR7=1）.IfSR0=0,thenPOCwillnotinterrupt.TheotherbitsofSRarenotusedandempty.

（4）ThetransferofacharactertoPOCviathesystembusproceedsasfollows.

Inpollingmode,SR0isalways0.

TheprocessorselectsSRbyaccessingtherelativeaddress,thenreadsSRregister,ifSR7=1,theprocessorselectsBRandwritesacharacterintoBR,thenprocessorclearsSR7toindicatethatthenewcharacterhasbeenwrittenintoBRandnotprintedyet.WhenPOCdetectsthatSR7issetto0,POCthenproceedstostartthehandshakingoperationswiththeprinter.Aftersendingcharactertoprinter,POCsetstheSR7to1,whichindicatesPOCisreadytoreceiveanothercharacterfromtheprocessor.Thetransfercyclecannowrepeat.DuringthehandshakingoperationsbetweenPOCandprinter,theprocessorcontinuestofetchandexecuteinstructions.IfithappenstoreadSR,itwillfindSR7=0andhencewillnotattempttosendanothercharactertothePOC.

Ininterruptmode,SR0isalways1.

Aftersendingcharactertoprinter,POCsetstheSR7to1,sinceSR0=1,theinterruptrequestsignal（IRQ）issetto0,whichindicateaneffectiveinterruptsignaltotheprocessor.WhentheprocessordetectstheeffectiveIRQsignal,theprocessordirectlyselectsBRandwritesacharacterintoBR,andthentheprocessorsetstheSR7to0,whichindicatesthatthenewcharacterhasbeenwrittenintoBRandnotprintedyet.WhenPOCdetectsthatSR7issetto0,POCthenproceedstostartthehandshakingoperationswiththeprinter.Aftersendingcharactertoprinter,POCsetstheSR7to1,whichindicatesPOCisreadytoreceiveanothercharacterfromtheprocessor.Thetransfercyclecannowrepeat.DuringthehandshakingoperationsbetweenPOCandprinter,theprocessordoesnottrytoaccessPOCuntilitreceivestheinterruptrequestsignal.

3.Theoverallconnectionexpressedinthetopmoduleform

Figure3Theoverallconnectionexpressedinthetopmoduleform

Inordertobeeasytodebug,someinsidesignalsandregistersaresetasoutputsignals.Infact,wejustonlyneedclk,clk2,reset,csandPDtobeoutsidesignals.

Signalsorregisters

Function

clk

ClockofCPUandPOC

clk2

ClockofPrinter

reset

Resetwhenreset=0

cs

cs=0:

pollingmode;cs=1:

interruptmode

PD

Datatobeprinted

Table1Theexplicationoftheoutsidesignals

4.Designdescriptionofthesimulationinputwaveforms

Asisshownintable1，4simulationinputsignalsareneeded.

（1）clkClockofCPUandPOC.

（2）clk2ClockofPrinter,fasterthanclk.

（3）resetResetwhenreset=0.

（4）cscs=0:

pollingmode;cs=1:

interruptmode.

5.Simulationresults

（1）Inpollingmode,cs=0,SR0isalways0.

（2）Ininterruptmode,cs=1,SR0isalways1.

6.ConclusionsandDiscussions

POC,paralleloutputcontroller,playsaroleasaninterfacebetweenCPUandtheprinter.Asisshownabove,thetwosimulationwavesrevealthatthisdesignmeetstherequirements.

Inmydesign,allthecodesaremyoriginalworks.IhavewrittenthemoduleProcessortohelpcompletingsimulation,whichneedmorecodesanddebuggingtocooperatewiththeworkofPOC.EventhereisalreadyaschematicforthemodulePrinterintheteachingmaterial,IstillhavetodomoreworktofinishthismodulebecausethesoftwareIuseisISEwhosedevicesisdifferentfromthoseofQuartusII.

Theprocedureofdesignhelpsmeunderstandtheworkingprincipleofinterface.InthethirdtermofGrade2didwelearnsomethingaboutcomputerinterfaceinthecourseMicrocomputer.AndthecourseCOAhasreferredtoit,too.HereIusewhatIhavelearnedtodesignthisprogramandachievealot.

Inthisprogram,IusetheEDAsoftwareISEandVeriloghardwarelanguagetodesignthosethreemodulesandIsim,whichisamoduleofISE,andVHDLlanguageforsimulation.Asaresult,Ibecomemorefamiliarwiththeuseofhardwaredescriptionlanguage.

Appendix

------------------------------CPU------------------------------

modulePOC_CPU（

outputRW,

outputADDR,

output[7:

0]POCDin,

inputreset,

inputCLK,

input[7:

0]POCDout,

inputIRQ

）;

regADDR;

reg[7:

0]POCDin;

regRW;

regt1;

regt2;

reg[7:

0]n;//t为标记

always@（posedgeCLK）

begin

if（reset==0）

begin

t1<=0;

t2<=0;

n<=8'b00000000;

RW<=0;

ADDR<=0;

POCDin<=8'b00000000;

end

elseif（IRQ==0&&t2==0）//中断方式SR0=1，收到中断请求信号；

begin

ADDR<=1;

RW<=1;

POCDin<=8'b00000101+n;

t2<=1;

end

elseif（t2==1）

begin

ADDR<=0;

RW<=1;

POCDin<=8'b00000001;

t2<=0;

n<=n+1;

end

elseif（RW==1&&POCDin==8'b00000001）beginRW<=0;end

else//查询方式

begin

//ADDR<=0;RW<=0;

if（RW==0&&POCDout==8'b10000000&&t1==0）

//查询方式SR0=0，SR7=1;

begin

ADDR<=1;

RW<=1;

POCDin<=8'b00000101+n;

t1<=1;

end

if（POCDout==8'b10000000&&t1==1）

//查询方式SR0=0，已完成数据传递，将把SR7置为0；

begin

ADDR<=0;

RW<=1;

POCDin<=8'b00000000;

t1<=0;n<=n+1;

end

if（RW==1&&POCDin==8'b00000000）beginRW<=0;end

end

end

endmodule

------------------------------POC------------------------------

modulePOC_POC（

inputADDR,

input[7:

0]Din,

inputRW,

inputCLK,

inputreset,

inputcs,

outputIRQ,

outputTR,

output[7:

0]Dout,

output[7:

0]PD,

output[7:

0]SR,

output[7:

0]BR,

inputRDY

）;

regIRQ;

regTR;

reg[7:

0]Dout;

reg[7:

0]PD;

reg[7:

0]BR;

reg[7:

0]SR;

always@（posedgeCLK）

begin

if（reset==0）

begin

IRQ<=1;

TR<=0;

Dout<=8'b00000000;

PD<=8'b00000000;

BR<=8'b00000000;

SR<=8'b00000000;

end

elseif（cs==0）//查询方式

begin

if（ADDR==0&&RW==0）//读SR到CPU

begin

if（SR[7]==0&&RDY==1&&TR==0）

begin

PD<=BR;

TR<=1;

Dout<=SR;

end

elseif（TR==1）beginTR<=0;SR[7]<=1;Dout<=SR;end

elsebeginDout<=SR;end

end

if（ADDR==0&&RW==1）//写SRBR写入新数据后SR7被置为0

begin

SR<=Din;

end

/*if（ADDR==1&&RW==0）//读BR

begin

Dout<=BR;

end*/

if（ADDR==1&&RW==1）//写BR

begin

if（SR[7]==0&&RDY==1&&TR==0）

begin

BR<=Din;

PD<=BR;

TR<=1;

Dout<=8'b00000000;

end

elseif（TR==1）beginTR<=0;SR[7]<=1;BR<=Din;Dout<=8'b00000000;end

elsebeginBR<=Din;Dout<=8'b00000000;end

end

end

elseif（cs==1）//中断方式

begin

if（SR[0]==0）beginSR<=8'b00000001;end

elseif（ADDR==0&&RW==0）//读SR

begin

if（SR[7]==0&&RDY==1&&TR==0）

begin

PD<=BR;

TR<=1;

IRQ<=1;

Dout<=SR;

end

elseif（TR==1）beginTR<=0;IRQ<=0;SR[7]<=1;Dout<=SR;end

elsebeginDout<=SR;IRQ<=1;end

end

elseif（ADDR==0&&RW==1）//写SRBR写入新数据后SR7被置为0

begin

SR<=Din;

end

/*if（ADDR==1&&RW==0）//读BR

begin

Dout<=BR;

end*/

elseif（ADDR==1&&RW==1）//写BR此时SR7不可能为0

begin

if（SR[7]==0&&RDY==1&&TR==0）

begin

BR<=Din;

PD<=BR;

TR<=1;

IRQ<=1;

Dout<=8'b00000001;

end

elseif（TR==1）

begin

TR<=0;

IRQ<=0;

SR[7]<=1;

BR<=Din;

Dout<=8'b00000001;

end

//elseif（IRQ==0）beginIRQ<=1;end

elsebeginBR<=Din;IRQ<=1;Dout<=8'b00000001;end

end

end

end

endmodule

------------------------------Printer------------------------------