verilogquarters开发.docx
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verilogquarters开发.docx
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verilogquarters开发
ExerciseManual
for
DesigningwithQuartusII
Exercise1
Exercise1
Objectives:
∙CreateamultiplierusingtheMegaWizardPlug-inManager
∙Buildadesignusingtheschematiceditor
∙Analyzeandelaboratethedesigntocheckforerrors
PipelinedMultiplierDesign
Figure1
Step1(Opentheprojectandcreateschematicfile)
Inthisexercise,youwilluseaprojectwhichhasbeencreatedforyou.ThisexercisefocusesontheschematicdesigncapabilitiesinQuartus®II.
1.StartQuartusII4.1,ifnotalreadyopened.
2.Opentheproject
3.Createanewblankschematicfile.
4.Savetheschematicfileaspipenult.bdf.
WewillnowcreatethedesignshowninFigure1.
Step2(Buildan8x8multiplierusingtheMegaWizard®Plug-inManager)
1.WiththeMegaWizardPlug-InManager,hcreateamultiplieroutoftheLPM_MULTmegafunction(arithmeticfolder)usingthefollowingparameters:
Anyparameternotexplicitlydefinedbelowshouldbeleftinthedefaultsetting.TheparametersarelistedinorderastheyappearintheMegaWizard.
odevicefamily:
StratixII
ooutputfiletype:
VerilogHDL
ooutputfilename:
mult
odataaportwidth:
8
odatabportwidth:
8
o2stagepipeline(latency)
ogenerate.v&.bsffiles
Notethatthestepsyoujustwentthroughcouldbeappliedtoanydesignentrymethod.Onepossiblemodificationyoumighttryistochoosethesamelanguageoutputasyourdesignmodules.So,ifyouareusingVHDLmodules,aVHDLLPM_MULToutputcanbechosen.
2.Addthemultsymboltoyourblankschematic.
Step3(Createsymbolfor32worddeepRAMwritteninVHDL)
1.Openthefileram.vhd.
NoticethisisaVHDLfileinferringasingle-port32-bitsynchronousRAM.ThisfilecouldverywellbewritteninVerilog.ThisRAMblockcouldalsohavebeeneasilycreatedusingtheMegaWizard,selectingLPM_RAM_DP+inthestoragefolderortheRAM:
2-PORTinthememorycompilerfolder.
2.Createasymbolrepresentationofthisfilesothatyoucanaddittotheschematic.
3.Addtheramsymboltotheschematic.
Step4(AddPinstotheDesign)
Table1.PinList
Input
Output
clk1
q[15..0]
dataa[7..0]
datab[7..0]
wraddress[4..0]
rdaddress[4..0]
wren
1.Addtheinputandoutputpinslistedabovetotheschematic.
Step5(ConnectthePinsandBlocksintheSchematic)
1.Wiretheschematicasshownaboveusingwiresandbuses.
Rememberthatwiresaresinglebit(thin)linesandbusesaremulti-bit(thick)lines.
Step6(Saveandchecktheschematic)
1.Savetheschematic.
2.UsetheAnalysis&Synthesisoption(Processingmenuor
)tocheckthedesignforerrors.
Analysisandsynthesischecksthatallthedesignfilesarepresentandconnectionsaremadecorrectly.
ExerciseSummary
∙CompletedaschematicdesigninQuartusII
∙CreatedamultiplierusingtheMegaWizardPlug-InManager
∙GeneratedasymbolfrompreviouslycreatedHDLfile
∙CheckeddesignfilewithAnalysisandSynthesiscompileroption
ENDOFEXERCISE1
Exercise2
Exercise2
Objectives:
∙CreateaprojectusingtheNewProjectWizard
–Nametheproject
–Adddesignfiles
–Pickadevice
Step1(SetupProjectforQII4_1\Lab2_6)
1.StarttheNewProjectWizard….
Workingdirectory
Projectname
pipemult
Top-leveldesignentity
pipemult
Filestoaddtoproject
pipemult.bdf
mult.v
ram.vhd
EDATools
None
Devicefamily
StratixII
Devicepartnumber
EP2S15F484C3
2.Usethetableabovetocompletethewizard.
3.Thesummaryscreenshownaboveappearswhencompleted.ClickFinish.Theprojectisnowcreated.
ExerciseSummary
∙CreatedaprojectusingtheNewProjectWizard
∙Namedtheproject
∙Addeddesignfiles
∙Selectedtargetdevice
ENDOFEXERCISE2
Exercise3
Exercise3
Objectives:
∙Performfullcompilation
∙LocateinformationintheCompilationReport
∙Createanewrevisiontostorenewconstratintsettings
∙MakedesignconstraintsusingtheAssignmentEditor
∙AssignI/OpinsandperformI/OAnalysis
WithDSPBlocks(Default)
WithoutDSPBlocks
DeviceName
EP2S15F484C3
EP2S15F484C3
TotalALUTs
TotalDSPBlocksElements
TotalMemoryBits
WorstFmax
Step1(Compilethedesign)
1.Performafullcompilationonthedesign.
Step2(GatherinformationfromtheCompilationReportFile)
Bydefault,QuartusIIopenstheCompilationReportfileandhastheSummarySectionselected.Ifthisisnotopen,clickon
.
1.FromtheCompilationReport,recordtheTotalALUTs,Totalmemorybits,andDSPBlock9-bitelementsinthetableatthebeginningofthisexercise.Usethe“WithDSPBlocks(Default)”column.
2.FromtheTimingAnalyzerfolderintheCompilationReport.ClickonClockSetup:
‘clk1’tableundertheTimingAnalyzerfolder.Inthe“WithDSPBlocks(Default)”columnoftheexercisetable,recordtheworst(slowest)Actualfmaxfromtheclocktable.
Youwillinvestigatemoreaboutthetiminganalyzerfolderinthenextexercise.
Step3(Createanewrevisiontostoreconstraintchanges)
Inordertotrydifferentconstraintoptionsandseehowtheyaffectyourresults,QuartusIIhassupportforcreatingrevisions,witheachrevisionbuildinganewQSFfile.Youcanthenquicklycomparetheresultsofyourvariousrevisions.
1.Createanewprojectrevisioncalledpipemult_lebasedonthepipemult(default)revision.
Step4(ImplementthemultiplierinlogicelementsinsteadofaDSPBlock)
StratixandStratixIIDSPBlocksareavaluableresourceforimplementingmultiply,multiply-add,andmultiply-accumulatefunctionsintheFPGA.Theyprovideabetterusageofresourcesformultiplicationoverlogicelements.But,DSPBlocksarelimitedinnumber.Ifyoudesignhasmanymultipliers,itmaybeadvantageoustoimplementsmallerornon-speedcriticalmultipliersinlogicelementsinstead.ThiscanbedoneusinganoptionintheMegaWizardflow,oritcanbedoneonamultiplier-by-multiplierbasisusingtheAssignmentEditorlogicoption.
1.Right-clickonthemultsymbolintheschematicandlocatetotheassignmenteditor.
2.SettheDSPBlockBalancinglogicoption(constraint)assignmenttoLogicElements.
3.SavetheAssignmentEditorfile.
YourAssignmentEditorwindowshouldlooksimilartoabove.
Step5(Recompilethedesign)
1.Performanotherfullcompilation.
Step6(Determinetheperformanceofthedesign)
1.FromtheCompilationReport,recordtheTotalALUTs,Totalmemorybits,andDSPBlock9-bitelementsintheexercisetableabove.Usethe“WithoutDSPBlocks”column.
2.FromtheTimingAnalyzerfolderintheCompilationReport.ClickonClockSetup:
‘clk1’tableundertheTimingAnalyzerfolder.Inthe“WithoutDSPBlocks”columnoftheexercisetable,recordtheworstActualfmaxfromtheclocktable.
ItisprettycleartheDSPBlockscangreatlyimprovetiming,butaswithmanyoptionsthereisatrade-offwithregardstoresourceusage.Adesignwithalargenumberofmultipliersmayneedtouselogicelementsforthemodulesthatarenotspeed-critical.
Step7(UseAssignmentEditortomakegeneralpinplacementassignments)
1.IntheAssignmentEditortoolbar,makesuretheCategoryBar
andShowI/OBanksinColor
buttonsareenabled.
2.IntheCategorybar,clickonthePinbutton.
3.UndertheNodeFilter,unchecktheboxtoShowassignmentsforspecificnodes.
ThetopoftheAssignmentEditorwindowshouldlookasabove.
4.Forinputbusdataa,assignallbitsofthebustoI/Obank2withanI/Ostandardvoltagesettingof2.5V.
5.Forinputbusdatab,assignallbitsofthebustoI/Obank2withanI/Ostandardvoltagesettingof1.8V.
6.Foroutputbusq,assignallbitsofthebustoI/Obank3.LeavethedefaultI/Ostandard.
YourAssignmentEditorwindowshouldlookasshownabove.NoticethattheqoutputbusisshowninadifferentcolortoindicateitisbeingassignedtoadifferentI/OBankthanthedataaanddatabbusses.
7.SavetheAssignmentEditorfile.
Step8(AnalyzeI/Oassignments)
NowyouhavemadesimpleI/Oassignments,youcancheckthevalidityofthoseassignmentswithoutrunningafullcompilation.ThiswayyoucanquicklyandeasilyfindI/Oplacementissuesandcorrectthem.
1.RuntheI/OAssignmentAnalysisonthedesign.
Wastheanalysissuccessful?
CheckthemessagesintheMessagewindowortheFitterMessagesintheCompilationReport.Theyshouldreadasshownabove.
2.ReviewtheI/OAnalysisMessagesanddeterminethecauseoftheerror.Expandtheerrormessagestogetmoredetailastowhyeachpinofthedataabusisnotbeingplacedsuccessfully.
DeterminingthecauseoftheI/OplacementfailurerequiresreadingtheerrormessagescarefullyandhavingalittleunderstandingofStratixorgeneralFPGAI/Oblocks.Seeifyoucanunderstandandcorrectthecauseoftheerrorsonyourown.IfyoudonothavealotofStratixorFPGAexperience,then#’s3-5willshowyouhowcorrecttheerrors.
3.BringtheAssignmentEditortotheforegroundagain.
NoticethatyouhaveassigneddataaanddatabinputbussestoI/OBank2,butsetdifferentVCCIO(1.8&2.5)voltagelevelsforthem.StratixIIdevices,likeallAlteraFPGAfamilies,allowforonlyoneVCCIOperI/Obank.
4.ChangetheI/Ostandardforthedatabbusto2.5V,likedataa.
5.SavetheAssignmentEditorandre-runtheI/OAssignmentAnalysis.
SeehowquicklyandeasilyyoucancheckyouI/Oplacementassignmentswithoutrunningafullcompilation!
Step9(Back-annotatepinassignmentstolockplacement)
Thisisthestepyouwoulduseonceyouhaveproducedaverifiedpin-outtobeginboarddesig
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