StratixVGXGSESchematicReviewWorksheet.docx
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StratixVGXGSESchematicReviewWorksheet.docx
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StratixVGXGSESchematicReviewWorksheet
Stratix®VGX,GSandEDeviceSchematicReviewWorksheet
ThisdocumentisintendedtohelpyoureviewyourschematicandcomparethepinusageagainsttheStratixVE,GS,andGXDeviceFamilyPinConnectionGuidelines(PDF)version1.4andotherreferencedliteratureforthisdevicefamily.ThetechnicalcontentisdividedintofocusareassuchasFPGApowersupplies,transceiverpowersuppliesandpinusage,configuration,andFPGAI/O,andexternalmemoryinterfaces.
Withineachfocusarea,thereisatablethatcontainsthevoltageorpinnameforallofthededicatedanddualpurposepinsforthedevicefamily.Insomecases,thedevicedensityandpackagecombinationmaynotincludesomeofthepinsshowninthisworksheet,youshouldcrossreferencewiththepin-outfileforyourspecificdevice.Linkstothedevicepin-outfilesareprovidedatthetopofeachsection.
Beforeyoubeginusingthisworksheettoreviewyourschematicandcommittoboardlayout,Alterahighlyrecommends:
1)ReviewthelatestversionoftheStratixVErrataSheet(PDF)andtheKnowledgeDatabaseforStratixVDeviceKnownIssuesandStratixVDeviceHandbookKnownIssues.
2)CompileyourdesignintheQuartus®IIsoftwaretocompletion.
Forexample,therearemanyI/OrelatedplacementrestrictionsandVCCIOrequirementsfortheI/Ostandardsusedinthedevice.Ifyoudonothaveacompleteproject,thenataminimumatoplevelprojectshouldbeusedwithallI/Opinsdefined,placed,andapplyalloftheconfigurableoptionsthatyouplantouse.AllI/Orelatedmegafunctionsshouldalsobeincludedintheminimalproject,including,butnotlimitedto,externalmemoryinterfaces,transceiverIP,PLLs,altlvds,andaltddio.TheI/OAnalysistoolinthePinPlannercanthenbeusedontheminimalprojecttovalidatethepinoutintheQuartusIIsoftwaretoassuretherearenoconflictswiththedevicerulesandguidelines.
WhenusingtheI/OAnalysistoolyoumustensuretherearenoerrorswithyourpinout.Additionally,youshouldcheckallwarningandcriticalwarningmessagestoevaluatetheirimpactonyourdesign.Youcanrightclickyourmouseoveranywarningorcriticalwarningmessageandselect“Help”.ThiswillbringopenanewHelpwindowwithfurtherinformationonthecauseofthewarning,andtheactionthatisrequired.
Forexample,thefollowingwarningisgeneratedwhenaPLLisdrivenbyaglobalnetworkwherethesourceisavaliddedicatedclockinputpin,butthepinisnotonededicatedtotheparticularPLL:
Warning:
PLL"
Info:
InputportINCLK[0]ofnode"
Thehelpfileprovidesthefollowing:
CAUSE:
ThespecifiedPLL'sinputclockisnotdrivenbyadedicatedinputpin.Asaresult,theinputclockdelaywillnotbefullycompensatedbythePLL.Additionally,jitterperformancedependsontheswitchingrateofotherdesignelements.Thiscanalsooccurifaglobalsignalassignmentisappliedtotheclockinputpin,whichforcestheclocktousethenon-dedicatedglobalclocknetwork.
ACTION:
Ifyouwantcompensationofthespecifiedinputclockorbetterjitterperformance,connecttheinputclockonlytoaninputpin,orassigntheinputpinonlytoadedicatedinputclocklocationforthePLL.Ifyoudonotwantcompensationofthespecifiedinputclock,thensetthePLLtoNoCompensationmode.
Whenassigningtheinputpintotheproperdedicatedclockpinlocation,refertoClockNetworksandPLLsinStratixVDevices(PDF)fortheproperportmappingofdedicatedclockinputpinstoPLLs.
TherearemanyreportsavailableforuseafterasuccessfulcompilationorI/Oanalysis.Forexample,youcanusethe“AllPackagePins”and“I/OBankUsage”reportswithintheCompilation–Fitter–ResourceSectiontoseealloftheI/OstandardsandI/Oconfigurableoptionsthatareassignedtoallofthepinsinyourdesign,aswellasviewtherequiredVCCIOforeachI/Obank.Thesereportsmustmatchyourschematicpinconnections.
Thereviewtablehasthefollowingheading:
Plane/Signal
SchematicName
ConnectionGuidelines
Comments/Issues
Thefirstcolumn(Plane/Signal)liststheFPGAvoltageorsignalpinname.Youshouldonlyeditthiscolumntoremovededicatedordualpurposepinnamesthatarenotavailableforyourdevicedensityandpackageoption.
Thesecondcolumn(SchematicName)isforyoutoenteryourschematicname(s)forthesignal(s)orplaneconnectedtotheFPGApin(s).
Thethirdcolumn(ConnectionGuidelines)shouldbeconsidered“readonly”asthiscontainsAltera’srecommendedconnectionguidelinesforthevoltageplaneorsignal.
Thefourthcolumn(Comments/Issues)isanareaprovidedasa“notepad”foryoutocommentonanydeviationsfromtheconnectionguidelines,andtoverifyguidelinesaremet.Inmanycasestherearenotesthatprovidefurtherinformationanddetailthatcomplimenttheconnectionguidelines.
Hereisanexampleofhowtheworksheetcanbeused:
Plane/Signal
SchematicName
ConnectionGuidelines
Comments/Issues
VCC
+0.85V
Connectedto+0.85Vplane,noisolationisnecessary.
Missinglowandmediumrangedecoupling,checkPDN.
SeeNotes(1-1)(1-2).
LegalNote:
PLEASEREVIEWTHEFOLLOWINGTERMSANDCONDITIONSCAREFULLYBEFOREUSINGTHISSCHEMATICREVIEWWORKSHEET(“WORKSHEET”)PROVIDEDTOYOU.BYUSINGTHISWORKSHEET,YOUINDICATEYOURACCEPTANCEOFSUCHTERMSANDCONDITIONS,WHICHCONSTITUTETHELICENSEAGREEMENT("AGREEMENT")BETWEENYOUANDALTERACORPORATIONORITSAPPLICABLESUBSIDIARIES("ALTERA").
1.SubjecttothetermsandconditionsofthisAgreement,Alteragrantstoyou,fornoadditionalfee,anon-exclusiveandnon-transferablerighttousethisWorksheetforthesolepurposeofverifyingthevalidityofthepinconnectionsofanAlteraprogrammablelogicdevice-baseddesign.YoumaynotusethisWorksheetforanyotherpurpose.TherearenoimpliedlicensesgrantedunderthisAgreement,andallrights,exceptforthosegrantedunderthisAgreement,remainwithAltera.
2.Alteradoesnotguaranteeorimplythereliability,orserviceability,ofthisWorksheetorotheritemsprovidedaspartofthisWorksheet.ThisWorksheetisprovided'ASIS'.ALTERADISCLAIMSALLWARRANTIES,EXPRESSORIMPLIED,INCLUDINGTHEIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENT.ALTERAHASNOOBLIGATIONTOPROVIDEYOUWITHANYSUPPORTORMAINTENANCE.
3.InnoeventshalltheaggregateliabilityofAlterarelatingtothisAgreementorthesubjectmatterhereofunderanylegaltheory(whetherintort,contract,orotherwise),exceedOneHundredUS Dollars(US$100.00).InnoeventshallAlterabeliableforanylostrevenue,lostprofits,orotherconsequential,indirect,orspecialdamagescausedbyyouruseofthisWorksheetevenifadvisedofthepossibilityofsuchdamages.
4.ThisAgreementmaybeterminatedbyeitherpartyforanyreasonatanytimeupon30-days’priorwrittennotice.ThisAgreementshallbegovernedbythelawsoftheStateofCalifornia,withoutregardtoconflictoflaworchoiceoflawprinciples.YouagreetosubmittotheexclusivejurisdictionofthecourtsintheCountyofSantaClara,StateofCaliforniafortheresolutionofanydisputeorclaimarisingoutoforrelatingtothisAgreement.Thepartiesherebyagreethatthepartywhoisnotthesubstantiallyprevailingpartywithrespecttoadispute,claim,orcontroversyrelatingtothisAgreementshallpaythecostsactuallyincurredbythesubstantiallyprevailingpartyinrelationtosuchdispute,claim,orcontroversy,includingattorneys'fees.FailuretoenforceanytermorconditionofthisAgreementshallnotbedeemedawaiveroftherighttolaterenforcesuchtermorconditionoranyothertermorconditionoftheAgreement.
BYUSINGTHISWORKSHEET,YOUACKNOWLEDGETHATYOUHAVEREADTHISAGREEMENT,UNDERSTANDIT,ANDAGREETOBEBOUNDBYITSTERMSANDCONDITIONS.YOUANDALTERAFURTHERAGREETHATITISTHECOMPLETEANDEXCLUSIVESTATEMENTOFTHEAGREEMENTBETWEENYOUANDALTERA,WHICHSUPERSEDESANYPROPOSALORPRIORAGREEMENT,ORALORWRITTEN,ANDANYOTHERCOMMUNICATIONSBETWEENYOUANDALTERARELATINGTOTHESUBJECTMATTEROFTHISAGREEMENT.
Index
SectionI:
Power
SectionII:
Configuration
SectionIII:
Transceiver
SectionIV:
I/O
a:
ClockPins
b:
DedicatedandDualPurposePins
c:
DualPurposeDifferentialI/Opins
SectionV:
ExternalMemoryInterfacePins
a:
DDR/2InterfacePins
b:
DDR/2TerminationGuidelines
c:
DDR3InterfacePins
d:
DDR3TerminationGuidelines
e:
QDRII/+Interfacepins
f:
QDRII/+TerminationGuidelines
SectionVI:
DocumentRevisionHistory
SectionI:
Power
Documentation:
StratixVDevices
StratixVPinOutFiles
StratixVE,GS,GXDeviceFamilyPinConnectionGuidelines(PDF)
StratixVEarlyPowerEstimator
StratixVEarlyPowerEstimatorUserGuide(PDF)
PowerDeliveryNetwork(PDN)ToolForStratixVDevices
Device-SpecificPowerDeliveryNetwork(PDN)ToolUserGuide(PDF)
PowerPlayPowerAnalyzerSupportResources
AlteraBoardDesignResourceCenter(Generalboarddesignguidelines,PDNdesign,isolation,tools,andmore)
AN583:
DesigningPowerIsolationFilterswithFerriteBeadsforAlteraFPGAs(PDF)
AN597:
GettingStartedFlowforBoardDesigns(PDF)
ErrataSheeta
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