第4章VerilogHDL代码EDA技术.docx
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第4章VerilogHDL代码EDA技术.docx
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第4章VerilogHDL代码EDA技术
EDA技术
第四章VerilogHDL代码
第一节数字电路
一、8位D触发器
功能描述:
8位D触发器,输出电平在时钟的驱动下跟踪输入电平。
//-----------------------------------------------------------------------------------------------
//学号:
//作者:
//Module:
Dff
//Filename:
Dff.v
//功能描述:
D触发器
//-----------------------------------------------------------------------------------------------
`timescale10ns/10ns
moduleDff(
clock,
reset,
data_in,
dff_out
);
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
inputclock;
inputreset;
input[7:
0]data_in;
output[7:
0]dff_out;
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
wireclock;
wirereset;
wire[7:
0]data_in;
wire[7:
0]dff_out;
//-----------------------------------------------------------------------------------------------
//InternalDeclaration
//-----------------------------------------------------------------------------------------------
reg[7:
0]dff;
//-----------------------------------------------------------------------------------------------
//MainBlock
//-----------------------------------------------------------------------------------------------
always@(posedgeresetorposedgeclock)
begin
if(reset)dff<=8’b0;
elsedff<=data_in;
end
assigndff_out=dff;
endmodule
二、计数器
功能描述:
4位10进制计数器
//-----------------------------------------------------------------------------------------------
//学号:
//作者:
//Module:
4_counter
//Filename:
4_counter.v
//功能描述:
4位10进制计数器
//-----------------------------------------------------------------------------------------------
`timescale10ns/10ns
module4_counter(
clock,
reset,
cnt_out
);
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
inputclock;
inputreset;
output[3:
0]cnt_out;
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
wireclock;
wirereset;
wire[3:
0]cnt_out;
//-----------------------------------------------------------------------------------------------
//InternalDeclaration
//-----------------------------------------------------------------------------------------------
Reg[3:
0]cnt;
//-----------------------------------------------------------------------------------------------
//MainBlock
//-----------------------------------------------------------------------------------------------
always@(posedgeresetorposedgeclock)
begin
if(reset)cnt<=0;
elsebegin
if(cnt==4’b1001)cnt<=0;
elsecnt<=cnt+1;
end
end
assigncnt_out=cnt;
endmodule
三、移位寄存器
功能描述:
8位移位寄存器,每次循环右移2位,控制端:
=0时锁存,=1时移位。
//-----------------------------------------------------------------------------------------------
//学号:
//作者:
//Module:
8_shifter
//Filename:
8_shifter.v
//功能描述:
8位移位寄存器
//-----------------------------------------------------------------------------------------------
`timescale10ns/10ns
module8_shifter(
clock,
reset,
control_in,
data_in,
data_out
);
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
inputclock;
inputreset;
inputcontrol_in;
input[7:
0]data_in;
output[7:
0]data_out;
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
wireclock;
wirereset;
wirecontrol_in;
wire[7:
0]data_in;
wire[7:
0]data_out;
//-----------------------------------------------------------------------------------------------
//InternalDeclaration
//-----------------------------------------------------------------------------------------------
reg[7:
0]data;
//-----------------------------------------------------------------------------------------------
//MainBlock
//-----------------------------------------------------------------------------------------------
always@(posedgeresetorposedgeclock)
begin
if(reset)data<=0;
elsebegin
if(control_in==0)data<=data_in;
elsedata<={data[1:
0],data[7:
2]};
end
end
assigndata_out=data;
endmodule
四、数据选择器
功能描述:
4通道数据选择器,选择端位数:
2,数据位宽度:
4
//-----------------------------------------------------------------------------------------------
//学号:
//作者:
//Module:
4_1selector
//Filename:
4_1selector.v
//功能描述:
4通道数据选择器
//-----------------------------------------------------------------------------------------------
`timescale10ns/10ns
module4_1selector(
//clock,
//reset,
select_in,
channel1_in,
channel2_in,
channel3_in,
channel4_in,
data_out
);
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
//inputclock;
//inputreset;
input[1:
0]select_in;
input[3:
0]channel1_in;
input[3:
0]channel2_in;
input[3:
0]channel3_in;
input[3:
0]channel4_in;
output[3:
0]data_out;
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
//wireclock;
//wirereset;
wire[1:
0]select_in;
wire[3:
0]channel1_in;
wire[3:
0]channel2_in;
wire[3:
0]channel3_in;
wire[3:
0]channel4_in;
wire[3:
0]data_out;
//-----------------------------------------------------------------------------------------------
//InternalDeclaration
//-----------------------------------------------------------------------------------------------
reg[3:
0]data;
//-----------------------------------------------------------------------------------------------
//MainBlock
//-----------------------------------------------------------------------------------------------
always@(select_inorchannel1_inorchannel2_inorchannel3_inorchannel4_in)
begin
case(select_in)
2’b00:
data=channel1_in;
2’b01:
data=channel2_in;
2’b10:
data=channel3_in;
default:
data=channel4_in;
endcase
end
assigndata_out=data;
/*assigndata_out=(select_in==2’b00)?
channel1_in:
((select_in==2’b01)?
channel2_in:
((select_in==2’b10)?
channel3_in:
channel4_in
)
);
*/
endmodule
五、编码器
功能描述:
4-2线编码器,4位输入,2位输出,1位错误检测输出
//-----------------------------------------------------------------------------------------------
//学号:
//作者:
//Module:
4_2encoder
//Filename:
4_2encoder.v
//功能描述:
8-3线编码器
//-----------------------------------------------------------------------------------------------
`timescale10ns/10ns
module4_2encoder(
//clock,
//reset,
data_in,
error_out,
encoder_out
);
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
//inputclock;
//inputreset;
input[3:
0]data_in;
outputerror_out;
output[1:
0]encoder_out;
//-----------------------------------------------------------------------------------------------
//InterfaceDeclaration
//-----------------------------------------------------------------------------------------------
//wireclock;
//wirereset;
Wire[3:
0]data_in;
Wireerror_out;
Wire[1:
0]encoder_out;
//-----------------------------------------------------------------------------------------------
//InternalDeclaration
//-----------------------------------------------------------------------------------------------
Reg[1:
0]encoder;
//-----------------------------------------------------------------------------------------------
//MainBlock
//-----------------------------------------------------------------------------------------------
//encoder_out
always@(data_in)
begin
case(data_in)
4’b0001:
encoder=2’b00;
4’b0010:
encoder=2’b01;
4’b0100:
encoder=2’b10;
4’b1000:
encoder=2’b11;
default:
encoder=2’b00;
endcase
end
assignencoder_out=encoder;
//error_out
assignerror_out=(data_in==4’b0001||data_in==4’b0010||
data_in==4’b0100||data_in==4’b1000)?
0:
1’b1;
endmodule
第二节状态机
功能:
控制模块工作流程,相当于模块的骨架,对整个模块的功能起控制和协调作用,每个模块module一般只使用一个状态机。
分类:
(1)Moore状态机:
时序逻辑的输出仅取决于当前状态;
(2)Mealy状态机:
时序逻辑的输出不仅取决于当前状态,还取决于输入。
一、Moore状态机
//-----------------------------------------------------------------------------------------------
//InternalDeclaration
//-----------------------------------------------------------------------------------------------
reg[1:
0]state;
//-----------------------------------------------------------------------------------------------
//ParameterDeclaration
//-----------------------------------------------------------------------------------------------
parameterIDLE=2’b00,
STATE1=2’b01,
STATE2=2’b10,
BLOCK_END=2’b11;
//-----------------------------------------------------------------------------------------------
//MainBlock
//-----------------------------------------------------------------------------------------------
always@(posedgeresetorposedgeclock)
begin
if(reset)state<=IDLE;
elsebegin
case(state)
IDLE:
state
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