ComputersStructures ComputersElectrical Engineering.docx
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ComputersStructures ComputersElectrical Engineering.docx
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ComputersStructuresComputersElectricalEngineering
5
PerformanceevaluationandoptimaldesignforFPGA-baseddigit-serialDSPfunctions OriginalResearchArticle
Computers&ElectricalEngineering,Volume29,Issue2,March2003,Pages357-377
HanhoLee,GeraldE.Sobelman
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AbstractAbstract|Figures/TablesFigures/Tables|ReferencesReferences
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ArticleOutline
1.Introduction
2.FPGAimplementationsandbasisofperformanceevaluation
2.1.Fieldprogrammablegatearrayimplementations
2.2.Basisofperformanceevaluation
3.Digit-serialarithmeticmacroblocks
3.1.Digit-serialadderandsubtractor
3.2.Bit-levelpipelineddigit-serialadderandsubtractor
3.3.Digit-serialmultipliers
3.3.1.Digit-levelpipelineddigit-serialmultiplier
3.3.2.Bit-levelpipelineddigit-serialmultiplier
3.4.Shiftregister
4.Digit-serialFIRfilters
4.1.Inverted-formdigit-serialFIRfilter
4.2.Canonical-formdigit-serialFIRfilter
5.Performancecomparisons
5.1.Comparisonofdigit-serialarchitecturesusingVHDLsynthesisandhandoptimizing
5.2.Comparisonofbit-serial,digit-serialandbit-parallelmultipliers
5.3.ComparisonofFIRfilters
6.Conclusions
Acknowledgements
References
Vitae
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Abstract
Asfieldprogrammablegatearray(FPGA)technologyhassteadilyimproved,FPGAsarenowviablealternativestoothertechnologyimplementationsforhigh-speedclassesofdigitalsignalprocessing(DSP)applications.Digit-serialDSParchitectureshavebeeneffectiveimplementationmethodforFPGAs.Inthiswork,amethodofimplementingdigit-serialDSParchitecturesonFPGAsispresented,andtheirperformanceisevaluatedwiththeobjectiveoffindinganddevelopingthemostefficientdigit-serialDSParchitecturesonFPGAs.Thispaperdiscussesareacostsandoperationaldelaysofthevariousdigit-serialDSPfunctionsandpresentsthearea/delaymodelsonXilinxXC4000-seriesFPGAs.Thesearea/delaymodelscanmakepredictionsofperformanceandhardwareresourceutilizationbeforealengthylayoutandsynthesisprocessisundertaken.Theresultsshowthatthearea/delaymodelsproposedherearevalidandthedigit-serialDSPdesignsarepromisingcandidatesforefficientFPGAimplementations.
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ModelingsoftwarerequirementwithtimingdiagramandSimulinkStateflow OriginalResearchArticle
InformationandSoftwareTechnology,Volume53,Issue5,May2011,Pages484-493
HongsukLee,KihyunChung,HyunsangPark,KyungheeChoi
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7
FPGA/DSP-basedimplementationofahigh-performancemulti-channelcounter OriginalResearchArticle
JournalofSystemsArchitecture,Volume55,Issues5-6,May-June2009,Pages310-316
F.Baronti,A.Lazzeri,R.Roncella,R.Saletti
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Towardsrealtimeimplementationofreconstructivesignalprocessingalgorithmsusingsystolicarrayscoprocessors OriginalResearchArticle
JournalofSystemsArchitecture,Volume56,Issue8,August2010,Pages327-339
A.Castillo-Atoche,D.Torres-Roman,Y.Shkvarko
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9
Integrationofdigitalsignalprocessingtechnologieswithpulsedelectronparamagneticresonanceimaging OriginalResearchArticle
JournalofMagneticResonance,Volume178,Issue2,February2006,Pages220-227
RandallH.Pursley,GhadiSalem,NallathambyDevasahayam,SankaranSubramanian,JanuszKoscielniak,MuraliC.Krishna,ThomasJ.Pohida
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Abstract
Theintegrationofmoderndataacquisitionanddigitalsignalprocessing(DSP)technologieswithFouriertransformelectronparamagneticresonance(FT-EPR)imagingatradiofrequencies(RF)isdescribed.TheFT-EPRsystemoperatesataLarmorfrequency(Lf)of300 MHztofacilitateinvivostudies.ThisrelativelylowfrequencyLf,inconjunctionwithour
10 MHzsignalbandwidth,enablestheuseofdirectfreeinductiondecaytime-lockedsubsampling(TLSS).Thisparticulartechniqueprovidesadvantagesbyeliminatingthetraditionalanalogintermediatefrequencydownconversionstagealongwiththecorrespondingnoisesources.TLSSalsoresultsinmanageablesampleratesthatfacilitatethedesignofDSP-baseddataacquisitionandimageprocessingplatforms.Morespecifically,weutilizeahigh-speedfieldprogrammablegatearray(FPGA)andaDSPprocessortoperformadvancedreal-timesignal
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