jtag的经典例子verilog.docx

jtag的经典例子verilog.docx

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jtag的经典例子verilog

jtag的经典例子

modulejtag（TCK,TMS,TDI,PROGRAM_COUNT,SFR_DATA,SOURCE_DI,XRAMDI,PROGDI,TRESET,SCLK,

//Output

TDO,//SOURCE_AJ,DESTIN_AJ,XRAMAJ,PROGAJ,DESTIN_DOJ,XRAMDOJ,

PROGRAM_COUNTJ,PROGDOJ,

NXRAMRJ,nXRAMWJ,NPSENJ,PROGWE,SFR_WRITEJ,Write_SFR,Read_SFR

Read_RAM,NDESTIN_WEJ,nDESTIN_WEJ,Write_PC,

ICReset,ICDisable,ICClock_Disable,ICClock_Enable

）;

//Input

inputTCK;

inputTMS;

inputTDI;

inputTRESET;

inputSCLK;//ICstopfeedbacksignalatstep_intostate

input[15:

0]PROGRAM_COUNT;//presentPCvalue

input[7:

0]SFR_DATA;

input[7:

0]SOURCE_DI;

input[7:

0]XRAMDI;

input[7:

0]PROGDI;

//Output

outputICReset;

outputICDisable;

outputICClock_Disable;

outputTDO;

//output[7:

0]SOURCE_AJ;

//output[15:

0]XRAMAJ;

//output[15:

0]PROGAJ;

//output[7:

0]DESTIN_DOJ;

//output[7:

0]XRAMDOJ;

//output[7:

0]PROGDOJ;

//output[15:

0]PROGRAM_COUNTJ;

outputWrite_PC;

outputNXRAMRJ;

outputnXRAMWJ;//NXRAMWJ,

outputNPSENJ;

outputWrite_SFR,SFR_WRITEJ;

outputRead_SFR;

outputRead_RAM;

outputnDESTIN_WEJ,NDESTIN_WEJ;

outputPROGWE;

//TestAccessPort（TAP）controllercontrolsthescanchainslogic.

//ThearchitectureoftheTAPdesignfullycompliedwiththeIEEE

//Standard1149.1-2090StandardTestAccessPortandBoundary-ScanArchitectur

//Forfurtherdetailsofit,pleaserefertothestandard.

//portdeclare

//databusandaddressbusfordifferentarea

wire[7:

0]DESTIN_DOJ;

wire[7:

0]XRAMDOJ;

wire[7:

0]PROGDOJ;

wire[7:

0]SOURCE_AJ;

wire[7:

0]DESTIN_AJ;

wire[15:

0]XRAMAJ;

wire[15:

0]PROGAJ;

//readandwriteflagfordifferentarea

regNXRAMRJ;

regnXRAMWJ,NXRAMWJ;

regNPSENJ;

regPROGWE;

regRead_SFR;

regRead_RAM;

regnDESTIN_WEJ,NDESTIN_WEJ;

regWrite_SFR;

regSFR_WRITEJ;

//Instructionregister:

IR_WIDTH8bits

reg[7:

0]InstructionReg;

reg[7:

0]InstructionRegLat;

//testdataregisters

reg[7:

0]IDCodeReg;

regBypassReg;

reg[7:

0]INTESTReg;

reg[7:

0]INTESTRegLat;

reg[7:

0]CtrlReg;

reg[7:

0]CtrlRegLat;

reg[7:

0]DataReg;

reg[7:

0]DataRegLat;

reg[15:

0]AddrReg;

reg[15:

0]AddrRegLat;

//setbreakpoint

reg[15:

0]BreakPointReg;

reg[15:

0]BreakPointLat1;

reg[15:

0]BreakPointLat2;

reg[15:

0]BreakPointLat3;

reg[15:

0]BreakPointLat4;

reg[15:

0]BreakPointLat5;

reg[15:

0]PcReg;

reg[15:

0]PcRegLat;

wire[15:

0]PROGRAM_COUNTJ;

//TDOselect

wireTDO;

regOutEnable;

regSelectedTDO;//dataout

wireOutSelect;//selectinstructionortestdataiscl

ockedout

wireInstructionOut;

wireDataPathOut;//testdataregisteroutport,select

whichtestdatapathtobeclockout

wireBypassOut;

wireIDCodeOut;

wireINTESTOut;

wireDataOut;

wireAddrOut;

wireCtrlOut;

wirePcOut;

wireBreakPointOut;

//ICDisableandresetflag

regICReset;

//wirereset;

wireICClock_Disable;

wireICClock_Enable;

regICDisable;

regICClock_Disable1;

regICClock_Disable2;

regICClock_Disable3;

wireStepin_flag;

reg[1:

0]Disable2_CNT;

regflag;

regflag_sample;

wireBreakpoint_flag;

//reg[1:

0]disable3_CNT;

//regdisable3_CNT_enable;

//break_pointinformationsandflags

//breakpointenable

regBreak1_enable;

regBreak2_enable;

regBreak3_enable;

regBreak4_enable;

regBreak5_enable;

wireBreak1Comp;

wireBreak2Comp;

wireBreak3Comp;

wireBreak4Comp;

wireBreak5Comp;

//disablebreakpoint

wireBreak1Disable;

wireBreak2Disable;

wireBreak3Disable;

wireBreak4Disable;

wireBreak5Disable;

//instructionselected

reg[19:

0]InstruDecode;

wireEXTESTSelected;

wireIDCODESelected;

wireINTESTSelected;

wireBYPASSSelected;

wireCTRLSelected;

wireDATASelected;

wireADDRSelected;

wirePCSelected;

wireWrite_PC;

wireBreakPoint1Selected;

wireBreakPoint2Selected;

wireBreakPoint3Selected;

wireBreakPoint4Selected;

wireBreakPoint5Selected;

wireBreakPoint_Disable;

wireBreak1DisableSelected;

wireBreak2DisableSelected;

wireBreak3DisableSelected;

wireBreak4DisableSelected;

wireBreak5DisableSelected;

//TAPstatemachineresetflag

wireTapReset;

//TAPstateregister:

4bits

reg[3:

0]TapState;

//UPDATA_IRFLAG

regIR_Update_flag;

//definetheTAPstates

parameterEXIT2_DR=4’h0;

parameterEXIT1_DR=4’h1;

parameterSHIFT_DR=4’h2;

parameterPAUSE_DR=4’h3;

parameterSELECT_IR_SCAN=4’h4;

parameterUPDATE_DR=4’h5;

parameterCAPTURE_DR=4’h6;

parameterSELECT_DR_SCAN=4’h7;

parameterEXIT2_IR=4’h8;

parameterEXIT1_IR=4’h9;

parameterSHIFT_IR=4’hA;

parameterPAUSE_IR=4’hB;

parameterRUN_TEST_IDLE=4’hC;

parameterUPDATE_IR=4’hD;

parameterCAPTURE_IR=4’hE;

parameterTEST_LOGIC_RESET=4’hF;

parameterDEVICE_IDCODE=1;

/************************************TAPStateMachine***********************************/

always@（posedgeTCKorposedgeTRESET）

begin:

p_TAPseq

if（TRESET）

TapState<=TEST_LOGIC_RESET;

else

begin:

TAPState

case（TapState）//synopsysfull_caseparallel_case

EXIT2_DR:

//4’h0

begin

if（TMS）

TapState<=UPDATE_DR;

else

TapState<=SHIFT_DR;

end

EXIT1_DR:

//4’h1

begin

if（TMS）

TapState<=UPDATE_DR;

else

TapState<=PAUSE_DR;

end

SHIFT_DR:

//4’h2

begin

if（TMS）

TapState<=EXIT1_DR;

end

PAUSE_DR:

//4’h3

begin

if（TMS）

TapState<=EXIT2_DR;

end

SELECT_IR_SCAN:

//4’h4

begin

if（TMS）

TapState<=TEST_LOGIC_RESET;

else

TapState<=CAPTURE_IR;

end

UPDATE_DR:

//4’h5

begin

if（TMS）

TapState<=SELECT_DR_SCAN;

else

TapState<=RUN_TEST_IDLE;

end

CAPTURE_DR:

//4’h6

begin

if（TMS）

TapState<=EXIT1_DR;

else

TapState<=SHIFT_DR;

end

SELECT_DR_SCAN:

//4’h7

begin

if（TMS）

TapState<=SELECT_IR_SCAN;

else

TapState<=CAPTURE_DR;

end

EXIT2_IR:

//4’h8

begin

if（TMS）

TapState<=UPDATE_IR;

else

TapState<=SHIFT_IR;

end

EXIT1_IR:

//4’h9

begin

if（TMS）

TapState<=UPDATE_IR;

else

TapState<=PAUSE_IR;

end

SHIFT_IR:

//4’hA

begin

if（TMS）

TapState<=EXIT1_IR;

end

PAUSE_IR:

//4’hB

begin

if（TMS）

TapState<=EXIT2_IR;

end

RUN_TEST_IDLE:

//4’hC

if（TMS）TapState<=SELECT_DR_SCAN;

UPDATE_IR:

//4’hD

begin

if（TMS）

TapState<=SELECT_DR_SCAN;

else

TapState<=RUN_TEST_IDLE;

end

CAPTURE_IR:

//4’hE

begin

if（TMS）

TapState<=EXIT1_IR;

else

TapState<=SHIFT_IR;

end

TEST_LOGIC_RESET:

//4’hF

if（!

TMS）TapState<=RUN_TEST_IDLE;

endcase

end//TAPState

end//p_TAPseq

/*always@（TapState）

if（TapState==`TEST_LOGIC_RESET）TapReset=1;

elseTapReset=0;*/

assignTapReset=（TapState==TEST_LOGIC_RESET）?

1:

0;

//assignreset=TapReset||ICReset;

/************************************TAPStateMachineend***********************************/

/***********************InstructionRegister***********************/

//Thefixedvalue0001isloadedintotheinstructionregisterduringtheCAPTURE_IRcontrollerstate.

always@（posedgeTCKorposedgeTapReset）

begin

if（TapReset）

InstructionReg<=0;//01;

elseif（TapState==CAPTURE_IR）

InstructionReg[7:

0]<=0;//8’h41;

elseif（TapState==SHIFT_IR）

InstructionReg[7:

0]<={TDI,InstructionReg[7:

1]};

end

always@（posedgeTapResetornegedgeTCK）

begin

if（TapReset）begin

InstructionRegLat=0;

flag=0;

IR_Update_flag=0;

end

elseif（TapState==UPDATE_IR）

begin

InstructionRegLat=InstructionReg;

IR_Update_flag=1;

if（InstructionRegLat[7:

6]==2’b10）

flag=!

flag;

else

flag=0;

end

else

IR_Update_flag=0;

end

//************************InstructionRegisterEnd*******************/

//********************instructiondecode***********************/

//instructionregLatselecttestdataregisterforoutput

always@（posedgeTapResetorposedgeSCLK）

begin

if（TapReset）

InstruDecode[19:

0]=20’h00000;

elsebegin

case（InstructionRegLat[7:

0]）

8’h40:

InstruDecode[19:

0]=20’h00001;//EXTESTSelected

8’h41:

InstruDecode[19:

0]=20’h00001<<1;//IDCODESelected

8’h42:

InstruDecode[19:

0]=20’h00001<<2;//PCSelected

8’H44:

InstruDecode[19:

0]=20’h00001<<3;//Write_PC

8’H45:

InstruDecode[19:

0]=20’h00001<<4;//INTESTSelected

8’h49:

InstruDecode[19:

0]=20’h00001<<5;//BreakPoint1Sele

cted

8’h4a:

InstruDecode[19:

0]=20’h00001<<6;//BreakPoint2Sele

cted

8’h4b:

InstruDecode[19:

0]=20’h00001<<7;//BreakPoint3Sele

cted

8’h4c:

InstruDecode[19:

0]=20’h00001<<8;//BreakPoint4Sele

cted

8’h4d:

InstruDecode[19:

0]=20’h00001<<9;//BreakPoint5Sele

cted

8’h50:

InstruDecode[19:

0]=20’h00001<<10;//BreakPoint_Dis

able

8’h51:

InstruDecode[19:

0]=20’h00001<<11;//Break1DisableSe

lected

8’h52:

InstruDecode[19:

0]=20’h00001<<12;//Break2DisableSe

lected

8’h53:

InstruDecode[19:

0]=20’h00001<<13;//Break3DisableSe

lected

8’h54:

InstruDecode[19:

0]=20’h00001<<14;//Break4DisableSe

lected

8’h55:

InstruDecode[19:

0]=20’h00001<<15;//Break5DisableSe

lected

8’h61:

InstruDecode[19:

0]=20’h00001<<16;//CTRLSelected

8’h62:

InstruDecode[19:

0]=20’h00001<<17;//DATASelected

8’h64:

InstruDecode[19:

0]=20’h00001<<18;//ADDRSelected

default:

InstruDecode[19:

0]=20’h00001<<19;//BYPASSSelected

endcase

end

end

assignEXTESTSelected=InstruDecode[0];

assignIDCODESelected=InstruDecode[1];

assignPCSelected=InstruDecode[2];

assignWrite_PC=InstruDecode[3];

assignINTESTSelected=InstruDecode[4];

assignBreakPoint1Selected=InstruDecode[5];

assignBreakPoint2Selected=InstruDecode[6];

assignBreakPoint3Selected=InstruDecode[7];

assignBreakPoint4Selected=InstruDecode[8];

assignBreakPoint5Selected=InstruDecode[9];

assignBreakPoint_Disable=InstruDecode[10];

assignBreak1DisableSelected=InstruDecode[11];

assignBreak2DisableSelected=InstruDecode[12];

assignBreak3DisableSelect