宁夏大学物电学院EDA期末考试考试程序.docx
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宁夏大学物电学院EDA期末考试考试程序.docx
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宁夏大学物电学院EDA期末考试考试程序
EDA复习资料
4位加计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt5is
port(clk:
instd_logic;
aa:
outstd_logic_vector(4downto1));
endcnt5;
architecturebehavofcnt5is
signalcqi:
std_logic_vector(4downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'thencqi<=cqi+1;endif;
endprocess;
aa<=cqi(4downto1);
endbehav;
6位右移寄存器
LIBRARYIEEE;--USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSREG6BIS
PORT(CLK,LOAD:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(5DOWNTO0);
Q:
outstd_logic_vector(5downto0));
ENDSREG6B;
ARCHITECTUREbehavOFSREG6BIS
SIGNALREG6:
STD_LOGIC_VECTOR(5DOWNTO0);
BEGIN
PROCESS(CLK,LOAD)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFLOAD='1'THENREG6<=DIN;
ELSEREG6(4DOWNTO0)<=REG6(5DOWNTO1);
ENDIF;
ENDIF;
ENDPROCESS;
Q<=REG6;
ENDbehav;
8位计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt8is
port(clk:
instd_logic;
aa:
outstd_logic_vector(7downto0));
endcnt8;
architecturebehavofcnt8is
signalcqi:
std_logic_vector(7downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'thencqi<=cqi+1;endif;
endprocess;
aa<=cqi(7downto0);
endbehav;
8位右移寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSREG6BIS
PORT(CLK,LOAD:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(7DOWNTO0);
Q:
outstd_logic_vector(7downto0));
ENDSREG6B;
ARCHITECTUREbehavOFSREG6BIS
SIGNALREG6:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
PROCESS(CLK,LOAD)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFLOAD='1'THENREG6<=DIN;
ELSEREG6(5DOWNTO0)<=REG6(6DOWNTO1);
ENDIF;
ENDIF;
ENDPROCESS;
Q<=REG6;
ENDbehav;
8位左移寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYr8IS
PORT(CLK,LOAD:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(7DOWNTO0);
Q:
outstd_logic_vector(7downto0));
ENDr8;
ARCHITECTUREbehavOFr8IS
SIGNALREG6:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
PROCESS(CLK,LOAD)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFLOAD='1'THENREG6<=DIN;
ELSEREG6(7DOWNTO1)<=REG6(6DOWNTO0);
ENDIF;
ENDIF;
ENDPROCESS;
Q<=REG6;
ENDbehav;
十进制减计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt10is
port(clk,rst,en:
instd_logic;
cq:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endcnt10;
architecturebehavofcnt10is
begin
process(clk,rst,en)
variablecqi:
std_logic_vector(3downto0);
begin
ifrst='1'thencqi:
="1001";
elsifclk'eventandclk='1'then
Ifen='1'then
ifcqi>0thencqi:
=cqi-1;
elsecqi:
=(others=>'0');
endif;
endif;
endif;
ifcqi=0thencout<='1';
elsecout<='0';
endif;
cq<=cqi;
endprocess;
endbehav;
16减计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt16is
port(clk,rst,en:
instd_logic;
cq:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endcnt16;
architecturebehavofcnt16is
begin
process(clk,rst,en)
variablecqi:
std_logic_vector(3downto0);
begin
ifrst='1'thencqi:
=(others=>'1');
elsifclk'eventandclk='1'then
ifen='1'then
ifcqi>0thencqi:
=cqi-1;
elsecqi:
=(others=>'1');
endif;
endif;
endif;
ifcqi=0thencout<='1';
elsecout<='0';
endif;
cq<=cqi;
endprocess;
endbehav;
16位加计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadder16bis
port(cin:
instd_logic;
a,b:
instd_logic_vector(15downto0);
s:
outstd_logic_vector(15downto0);
cout:
outstd_logic);
endadder16b;
architecturebehavofadder16bis
signalsint:
std_logic_vector(16downto0);
signalaa,bb:
std_logic_vector(16downto0);
begin
aa<='0'&a;bb<='0'&b;
sint<=aa+bb+cin;s<=sint(15downto0);cout<=sint(4);
endbehav;
32进制加计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt1is
port(clk,rst,en:
instd_logic;
cq:
outstd_logic_vector(4downto0);
cout:
outstd_logic);
endcnt1;
architecturebehavofcnt1is
begin
process(clk,rst,en)
variablecqi:
std_logic_vector(4downto0);
begin
ifrst='1'thencqi:
=(others=>'0');
elsifclk'eventandclk='1'then
ifen='1'then
ifcqi<31thencqi:
=cqi+1;
elsecqi:
=(others=>'0');
endif;
endif;
endif;
ifcqi=31thencout<='1';
elsecout<='0';
endif;
cq<=cqi;
endprocess;
endbehav;
32进制双向计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt24is
port(clk,en,u_d:
instd_logic;
cq:
outstd_logic_vector(4downto0));
endcnt24;
architecturebehavofcnt24is
signalcqi:
std_logic_vector(4downto0);
begin
process(clk,en,u_d)
begin
ifen='1'thencqi<=cqi;
elsifclk'eventandclk='1'then
ifu_d='1'thencqi<=cqi+1;
elsecqi<=cqi-1;
endif;
endif;
endprocess;
cq(4downto0)<=cqi;
endbehav;
JK触发器
libraryieee;
useieee.std_logic_1164.all;
entityjkis
port(j,k,clk:
instd_logic;
q,nq:
bufferstd_logic);
end;
architecturebhvofjkis
signalq_s,nq_s:
std_logic;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(j='0')and(k='1')then
q_s<='0';
nq_s<='1';
elsif(j='1')and(k='0')then
q_s<=notq;
nq_s<=notnq;
endif;
endif;
q<=q_s;nq<=nq_s;
endprocess;
endbhv;
半加器
libraryieee;
useieee.std_logic_1164.all;
entityadis
port(a,b:
instd_logic;
co,so:
OUTstd_logic);
endentityad;
architecturefh1ofadis
begin
so<=not(axor(notb));co<=aandb;
endarchitecturefh1;
两个数比较器
libraryieee;
useieee.std_logic_1164.all;
entitycomp_radis
port(a1,b1:
inbit;
q1:
outbit);
end;
architectureoneofcomp_radis
begin
process(a1,b1)
begin
ifa1>b1thenq1<='1';
elseq1<='0';
endif;
endprocess;
end;
注释:
a1b1输入
Q1输出
A1>b1得出q1=1
A1 三八译码器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitythree_eightis port(a,b,c: instd_logic; d0,d1,d2,d3,d4,d5,d6,d7: outstd_logic); endthree_eight; architectures_bofthree_eightis signalo_11,o_22,o_33: std_logic; begin process(a,b,c) begin o_11<=nota; o_22<=notb; o_33<=notc; endprocess; d0<=o_11ando_22ando_33; d1<=aando_22ando_33; d2<=o_11andbando_33; d3<=aandbando_33; d4<=o_11ando_22andc; d5<=aando_22andc; d6<=o_11andbandc; d7<=aandbandc; ends_b; 三个数比较器 libraryieee; useieee.std_logic_1164.all; entitycompis port(a1,b1,c1: std_logic_vector(3downto0); q: outstd_logic_vector(3downto0)); end; architectureoneofcompis signalq1,q2: std_logic_vector(3downto0); begin process(a1,b1,c1) begin ifa1>b1then q1<=a1; elseq1<=b1; endif; ifq1>=c1then q2<=q1; elseq2<=c1; endif; q<=q2; endprocess; end; 三态门 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYtri_sIS port(enable: INSTD_LOGIC; datain: INSTD_LOGIC_VECTOR(7DOWNTO0); dataout: OUTSTD_LOGIC_VECTOR(7DOWNTO0)); ENDtri_s; ARCHITECTUREbhvOFtri_sIS BEGIN PROCESS(enable,datain) BEGIN IFenable='1'THENdataout<=datain; ELSEdataout<="ZZZZZZZZ"; ENDIF; ENDPROCESS; ENDbhv; 三位全加计数器 libraryieee; useieee.std_logic_1164.all; entitysanjiais port(ain: instd_logic_vector(2downto0); bin: instd_logic_vector(2downto0); cin: instd_logic; dout: outstd_logic_vector(2downto0); eout: outstd_logic); endentity; architecturebjofsanjiais componentf_adder port(a,b,c: instd_logic; d,e: outstd_logic); endcomponent; signalf,g: std_logic; begin u1: f_adderportmap(a=>ain(0),b=>bin(0),c=>cin,d=>f,e=>dout(0)); u2: f_adderportmap(a=>ain (1),b=>bin (1),c=>f,d=>g,e=>dout (1)); u3: f_adderportmap(a=>ain (2),b=>bin (2),c=>g,d=>eout,e=>dout (2)); endarchitecture; 十进制加计数器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitycnt1is port(clk,rst,en: instd_logic; cq: outstd_logic_vector(3downto0); cout: outstd_logic); endcnt1; architecturebehavofcnt1is begin process(clk,rst,en) variablecqi: std_logic_vector(3downto0); begin ifrst='1'thencqi: =(others=>'0'); elsifclk'eventandclk='1'then ifen='1'then ifcqi<9thencqi: =cqi+1; elsecqi: =(others=>'0'); endif; endif; endif; ifcqi=9thencout<='1'; elsecout<='0'; endif; cq<=cqi; endprocess; endbehav; 四选一数据选择器 libraryieee; useieee.std_logic_1164.all; entitynux41is port(a,b,c,d: instd_logic; s: instd_logic_vector(1downto0); z: outstd_logic); endnux41; architectureaofnux41is begin process(s,a,b,c,d) begin casesis when"00"=>z<=a; when"01"=>z<=b; when"10"=>z<=c; when"11"=>z<=d; whenothers=>z<=null; endcase; endprocess; enda; 异步复位同步使能十进制加法计数 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitycout10is port(clk,rst,en: instd_logic; cq: outstd_logic_vector(3downto0); cout: outstd_logic); endcout10; architecturebehavofcout10is begin process(clk,rst,en) variablecqi: std_logic_vector(3downto0); begin ifrst='1'thencqi: =(others=>'0'); elsifclk'eventandclk='1'then ifen='1'then ifcqi<9thencqi: =cqi+1; elsecqi: =(others=>'0'); endif; endif; endif; ifcqi=9thencout<='1'; elsecout<='0'; endif; cq<=cqi; endprocess; endbehav; 四选一数据选择器 libraryieee; useieee.std_logic_1164.all; entitynux41is port(a,b,c,d: instd_logic; s: instd_logic_vector(1downto0); z: outstd_logic); endnux41; architectureaofnux41is begin process(s,a,b,c,d) begin casesis when"00"=>z<=a; when"01"=>z<=b; when"10"=>z<=c; when"11"=>z<=d; whenothers=>z<=null; endcase; endprocess; enda; JK触发器 libraryieee; useieee.std_logic_1164.all; entityjkis port(j,k,
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