首师大计组VHDL单周期CPU设计.docx
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首师大计组VHDL单周期CPU设计.docx
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首师大计组VHDL单周期CPU设计
首师大计组VHDL单周期CPU设计
顶层文件:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entityCPUis
port(
--rw_address:
outstd_logic_vector(4downto0);
--ra_address:
outstd_logic_vector(4downto0);
--rb_address:
outstd_logic_vector(4downto0);
--ra:
outstd_logic_vector(31downto0);
--rb:
outstd_logic_vector(31downto0);
--aluzero:
outstd_logic;
--pc_address:
outstd_logic_vector(31downto0);
clkzong:
instd_logic;
rst:
instd_logic;
--ALUout:
outstd_logic_vector(31downto0);
DMdata:
outstd_logic_vector(31downto0);
--RFwin:
outstd_logic_vector(31downto0);
--ALUinB:
outstd_logic_vector(31downto0);
--RegDst1,RegWrite1,ALUSrc1,MemtoReg1,MemWrite1,SEControl1:
outstd_logic;
--NPCControl1:
outstd_logic_vector(1downto0);
--ALUControl1:
outstd_logic_vector(2downto0);
jdb18:
outstd_logic_vector(31downto0);
jdb8:
outstd_logic_vector(31downto0);
jdb16:
outstd_logic_vector(31downto0);
jdb17:
outstd_logic_vector(31downto0);
Zhiling:
outstd_logic_vector(31downto0));
endCPU;
architectureBehavioralofCPUis
componentCU
port(
op:
instd_logic_vector(5downto0);
func:
instd_logic_vector(5downto0);
RegDst,RegWrite,ALUSrc,MemtoReg,MemWrite,SEControl:
outstd_logic;
NPCControl:
outstd_logic_vector(1downto0);
ALUControl:
outstd_logic_vector(2downto0));
endcomponent;
componentNPC
port(
input:
instd_logic_vector(31downto0);
offset:
instd_logic_vector(31downto0);
pc:
instd_logic_vector(31downto0);
nNPCcontrol:
instd_logic_vector(1downto0);
ALUZero:
instd_logic;
npc1:
outstd_logic_vector(31downto0));
endcomponent;
componentPC
port(clk,clr:
instd_logic;
pc_in:
instd_logic_vector(31downto0);
pc_out:
outstd_logic_vector(31downto0));
endcomponent;
componentdm
PORT(clka:
instd_logic;
wea:
instd_logic_vector(0downto0);
addra:
instd_logic_vector(7downto0);
dina:
instd_logic_vector(31downto0);
douta:
outstd_logic_vector(31downto0));
endcomponent;
componentim
port(a:
instd_logic_vector(7downto0);
spo:
outstd_logic_vector(31downto0));
endcomponent;
componentSE
port(
a:
instd_logic_vector(15downto0);
s:
instd_logic;
y:
outstd_logic_vector(31downto0));
endcomponent;
componentmux32
port(
A,B:
instd_logic_vector(31downto0);
s:
instd_logic;
Z:
outstd_logic_vector(31downto0));
endcomponent;
componentmux5
port(
A,B:
instd_logic_vector(4downto0);
s:
instd_logic;
Z:
outstd_logic_vector(4downto0));
endcomponent;
componentrf
port(clk,we:
instd_logic;
ra,rb,rw:
instd_logic_vector(4downto0);
rd:
instd_logic_vector(31downto0);
qa,qb:
outstd_logic_vector(31downto0);
jdb1,jdb2,jdb3,jdb4:
outstd_logic_vector(31downto0));
endcomponent;
componentalu
port(ALUA,ALUB:
instd_logic_vector(31downto0);--操作数
aluc:
instd_logic_vector(2downto0);--alu控制:
00加法,01减法,10或运算
alu_out:
outstd_logic_vector(31downto0);--alu输出
zero:
outstd_logic);--零标志位:
alu结果为零zero=1
endcomponent;
signalx4,x6,x7,x8,x9,x17:
STD_logic;--定义内部连接信号
signalx5:
std_logic_vector(0downto0);
signalx3,x13,x14,x15,x16,x18,x19,x20,xa,xb,xc,xd:
std_logic_vector(31downto0);
signalx1,x2:
std_logic_vector(31downto0);
signalx10:
std_logic_vector(1downto0);
signalx11:
std_logic_vector(2downto0);
signalx12:
std_logic_vector(4downto0);
begin
pc1:
PCPORTMAP(clk=>clkzong,clr=>rst,pc_in=>x1,pc_out=>x2);
im1:
IMPORTMAP(a=>x2(9downto2),spo=>x3);
cu1:
CUPORTMAP(op=>x3(31downto26),func=>x3(5downto0),RegDst=>x7,RegWrite=>x8,ALUSrc=>x9,MemtoReg=>x6,MemWrite=>x5(0),SEControl=>x4,NPCControl=>x10,ALUControl=>x11);
mux1:
MUX5PORTMAP(A=>x3(15downto11),B=>x3(20downto16),s=>x7,z=>x12);
rf1:
rfPORTMAP(clk=>clkzong,we=>x8,ra=>x3(25downto21),rb=>x3(20downto16),rw=>x12,rd=>x13,qa=>x14,qb=>x15,jdb1=>xa,jdb2=>xb,jdb3=>xc,jdb4=>xd);
alu1:
ALUPORTMAP(ALUa=>x14,ALUb=>x16,aluc=>x11,zero=>x17,ALu_out=>x18);
mux2:
mux32PORTMAP(a=>x15,b=>x19,s=>x9,z=>x16);
mux3:
mux32PORTMAP(a=>x18,b=>x20,s=>x6,z=>x13);
dm1:
DMPORTMAP(addra=>x18(7downto0),dina=>x15,wea=>x5,clka=>clkzong,douta=>x20);
npc2:
NPCPORTMAP(input=>x3,offset=>x19,pc=>x2,nNPCControl=>x10,ALUzero=>x17,NPC1=>x1);
se1:
seportmap(a=>x3(15downto0),s=>x4,y=>x19);
--ALUout<=x18;
DMdata<=x20;
--RFwin<=x13;
--ALUinB<=x16;
Zhiling<=x3;
--RegDst1<=x7;
--RegWrite1<=x8;
--ALUSrc1<=x9;
--MemtoReg1<=x6;
--MemWrite1<=x5(0);
--SEControl1<=x4;
--NPCControl1<=x10;
--ALUControl1<=x11;
--pc_address<=x1;
--aluzero<=x17;
--ra<=x14;
--rb<=x15;
jdb18<=xa;
jdb8<=xb;
jdb16<=xc;
jdb17<=xd;
--ra_address<=x3(25downto21);
--rb_address<=x3(20downto16);
--rw_address<=x12;
endBehavioral;
Pc:
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
16:
35:
0406/17/2014
--DesignName:
--ModuleName:
pc-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityPCis
port(clk,clr:
instd_logic;
pc_in:
instd_logic_vector(31downto0);
pc_out:
outstd_logic_vector(31downto0));
endPC;
architectureBehavioralofPCis
begin
process(clk,clr)begin
ifclr='1'then
pc_out<=X"00000000";
elseifclk'eventandclk='1'then
--shangshengyangengxin
pc_out<=pc_in;
endif;
endif;
endprocess;
endBehavioral;
Control:
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
16:
34:
3006/17/2014
--DesignName:
--ModuleName:
cu-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityCUis
port(
op:
instd_logic_vector(5downto0);
func:
instd_logic_vector(5downto0);
RegDst,RegWrite,ALUSrc,MemtoReg,MemWrite,SEControl:
outstd_logic;
NPCControl:
outstd_logic_vector(1downto0);
ALUControl:
outstd_logic_vector(2downto0));
endCU;
architectureBehavioralofCUis
signaladd,and1,addi,beq,j,sw,lw:
std_logic;
begin
process(op,func)begin
if(op="000000"andfunc="100000")thenadd<='1';and1<='0';addi<='0';beq<='0';j<='0';sw<='0';lw<='0';
elsif(op="000000"andfunc="100100")thenadd<='0';and1<='1';addi<='0';beq<='0';j<='0';sw<='0';lw<='0';
elsif(op="001000")thenadd<='0';and1<='0';addi<='1';beq<='0';j<='0';sw<='0';lw<='0';
elsif(op="000100")thenadd<='0';and1<='0';addi<='0';beq<='1';j<='0';sw<='0';lw<='0';
elsif(op="000010")thenadd<='0';and1<='0';addi<='0';beq<='0';j<='1';sw<='0';lw<='0';
elsif(op="101011")thenadd<='0';and1<='0';addi<='0';beq<='0';j<='0';sw<='1';lw<='0';
elsif(op="100011")thenadd<='0';and1<='0';addi<='0';beq<='0';j<='0';sw<='0';lw<='1';
elseNULL;
endif;
endprocess;
RegDst<=addiorlw;
RegWrite<=(addorand1oraddiorlw)and(notbeq);
ALUSrc<=addiorsworlw;
MemtoReg<=lw;
MemWrite<=sw;
SEControl<=sworlw;
NPCControl
(1)<=beq;
NPCControl(0)<=j;
ALUControl
(2)<='0';
ALUControl
(1)<=and1;
ALUControl(0)<=and1orbeq;
endBehavioral;
Mux:
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
16:
33:
3906/17/2014
--DesignName:
--ModuleName:
mux5-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitymux5is
port(
A,B:
instd_logic_vector(4downto0);
s:
instd_logic;
Z:
outstd_logic_vector(4downto0));
endmux5;
architectureBehavioralofmux5is
begin
Z<=awhens='0'
elseb;
endBehavioral;
寄存器:
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
16:
33:
0906/17/2014
--DesignName:
--ModuleName:
rf-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityrfis
port(clk,we:
instd_logic;
ra,rb,rw:
instd_logic_vector(4dow
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