计数器.docx
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- 上传时间:2023-08-05
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计数器.docx
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计数器
一、一般计数器
▪ENTITYwz6is
PORT(clk:
INStd_Logic;
▪q:
OUTStd_Logic_vector(3downto0));
▪ENDwz6;
▪ARCHITECTUREaOFwz6IS
▪signalq1:
std_logic_vector(3downto0);
▪BEGIN
▪process(clk)
▪begin
▪ifclk'eventandclk='1'then
▪q1<=q1+1;
▪endif;
▪q<=q1;
▪endprocess;
▪enda;
二、带进位输出——分频——数控分频
(1)带进位输出——分频
ENTITYfenpinIS
PORT(CLK:
INSTD_LOGIC;
Q:
outSTD_LOGIC_VECTOR(3DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDfenpin;
ARCHITECTUREfenOFfenpinIS
SIGNALQ1:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
ifq1="1111"
thenq1<="0000";co<='1';
elseq1<=q1+1;co<='0';
ENDIF;
endif;
ENDPROCESS;
q<=q1;
ENDfen;
(2)数控分频——乐曲演奏
①思路一:
0——D(归零法且:
设为信号则相当于用
清零,即最后状态能留住)
清零,即最后状态不能留住)
以上还要根据具体的语句
例1:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityskfp1is
port(clk:
instd_logic;
d:
instd_logic_vector(7downto0);
fout:
outstd_logic);
endskfp1;
architectureaofskfp1is
signalq:
std_logic_vector(7downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
q<=q+1;
endif;
ifq=dthenq<="00000000";fout<='1';
elsefout<='0';
endif;
endprocess;
enda;
仿真成功
而稍加改动,则
例2
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityskfp1is
port(clk:
instd_logic;
d:
instd_logic_vector(7downto0);
fout:
outstd_logic);
endskfp1;
architectureaofskfp1is
signalq:
std_logic_vector(7downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
q<=q+1;
ifq=dthenq<=”00000000”;fout<=‘1’;
elsefout<=’0’;
endif;
endif;
endprocess;
enda;
问题:
输入07,频率反而比33分得的频率低。
但如果不是数控分频,单是任意固定模数的计数器,则没有问题
若红笔改为下面,则成功
IFQ<=DTHEN
IFCLK'EVENTANDCLK='1'THEN
Q<=Q+1;CO<='0';
ENDIF;
ELSeQ<="00000000";CO<='1';
endif;
ENDPROCESS;
②思路2:
D——计数器满(预置补数法)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityskfpis
port(clk:
instd_logic;
d:
instd_logic_vector(7downto0);
fout:
outstd_logic);
endskfp;
architectureaofskfpis
signalq:
std_logic_vector(7downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifq="11111111"then
q<=d;fout<='1';
else
q<=q+1;fout<='0';
endif;
endif;
endprocess;
enda;
注:
仿真时,仿真时间要设的长一些,2微秒不行,10微秒可以,输入数据要设为二进制,十六进制不行(CYCLON系列),而7128系列可以设为十六进制。
以上仿真图,输入数据持续时间还应再长一些。
三、带使能端、进位输出端
ENTITYfenpin1IS
PORT(CLK,en:
INSTD_LOGIC;
Q:
outSTD_LOGIC_VECTOR(3DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDfenpin1;
ARCHITECTUREfenOFfenpin1IS
SIGNALQ1:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
ifen='1'then
IFCLK'EVENTANDCLK='1'THEN
ifq1="1111"
thenq1<="0000";co<='1';
elseq1<=q1+1;co<='0';
ENDIF;
endif;
endif;
ENDPROCESS;
q<=q1;
ENDfen;
四、十进制计数器(加法式、减法式)
1、模47加法式(任意模数)Cyclon仿真成功
LIBRARYIEEE;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYJS47IS
PORT(CLK:
INSTD_LOGIC;
QH,QL:
BUFFERSTD_LOGIC_VECTOR(3downto0));
ENDJS47;
ARCHITECTUREAOFJS47IS
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFQL="1001"THEN
QL<="0000";QH<=QH+1;
ELSIFQH="0100"ANDQL="0110"THEN
QH<="0000";QL<="0000";
ELSEQL<=QL+1;
ENDIF;
ENDIF;
ENDPROCESS;
ENDA;
2、模23减法式可显示
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityjs23_1is
port(clk:
instd_logic;
seg1:
outstd_logic_vector(6downto0);
seg2:
outstd_logic_vector(6downto0);
co:
outstd_logic);
endjs23_1;
architectureaofjs23_1is
signalq1:
std_logic_vector(4downto0);
signalrst:
std_logic;
signalBCD:
std_logic_vector(7downto0);
begin
process(clk)
begin
ifrst='1'thenq1<="10110";
elsifclk'eventandclk='1'then
q1<=q1-1;
endif;
endprocess;
rst<='1'whenq1="00000"else
'0';
co<=rst;
BCD<="00000000"WHENq1="00000000"else
"00000001"WHENq1="00000001"else
"00000010"WHENq1="00000010"else
"00000011"WHENq1="00000011"else
"00000100"WHENq1="00000100"else
"00000101"WHENq1="00000101"else
"00000110"WHENq1="00000110"else
"00000111"WHENq1="00000111"else
"00001000"WHENq1="00001000"else
"00001001"WHENq1="00001001"else
"00010000"WHENq1="00001010"else
"00010001"WHENq1="00001011"else
"00010010"WHENq1="00001100"else
"00010011"WHENq1="00001101"else
"00010100"WHENq1="00001110"else
"00010101"WHENq1="00001111"else
"00010110"WHENq1="00010000"else
"00010111"WHENq1="00010001"else
"00011000"WHENq1="00010010"else
"00011001"WHENq1="00010011"else
"00100000"WHENq1="00010100"else
"00100001"WHENq1="00010101"else
"00100010"WHENq1="00010110"else
"00000000";
seg1<="0111111"whenBCD(3downto0)="0000"else
"0000110"whenBCD(3downto0)="0001"else
"1011011"whenBCD(3downto0)="0010"else
"1001111"whenBCD(3downto0)="0011"else
"1100110"whenBCD(3downto0)="0100"else
"1101101"whenBCD(3downto0)="0101"else
"1111101"whenBCD(3downto0)="0110"else
"0000111"whenBCD(3downto0)="0111"else
"0000111"whenBCD(3downto0)="0111"else
"0000111"whenBCD(3downto0)="0111"else
"1111111"whenBCD(3downto0)="1000"else
"1101111"whenBCD(3downto0)="1001"else
"0000000";
seg2<="0111111"whenBCD(7downto4)="0000"else
"0000110"whenBCD(7downto4)="0001"else
"1011011"whenBCD(7downto4)="0010"else
"1001111"whenBCD(7downto4)="0011"else
"1100110"whenBCD(7downto4)="0100"else
"1101101"whenBCD(7downto4)="0101"else
"1111101"whenBCD(7downto4)="0110"else
"0000111"whenBCD(7downto4)="0111"else
"0000111"whenBCD(7downto4)="0111"else
"0000111"whenBCD(7downto4)="0111"else
"1111111"whenBCD(7downto4)="1000"else
"1101111"whenBCD(7downto4)="1001"else
"0000000";
enda;
3、模23(31减至8)计数器——倒计时
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityjishuis
port(clk:
instd_logic;
q:
outstd_logic_vector(4downto0));
endjishu;
architecturessofjishuis
signaloo:
std_logic_vector(4downto0);
begin
process(clk,oo)
begin
ifoo>="01001"then
ifclk'eventandclk='1'then
oo<=oo-1;
endif;
elseoo<="11111";
endif;
q<=oo;
endprocess;
endss;
五、占空比均匀、占空比可调计数器
(1)占空比均匀
ENTITYfenfenIS
PORT(CLK:
INSTD_LOGIC;
Q:
outSTD_LOGIC_VECTOR(3DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDfenfen;
ARCHITECTUREfenOFfenfenIS
SIGNALQ1:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
ifq1="1111"
thenq1<="0000";
elseq1<=q1+1;
ENDIF;
endif;
ENDPROCESS;
PROCESS(Q1)
BEGIN
IFQ1<="0111"
THENCO<='0';
ELSECO<='1';
ENDIF;
ENDPROCESS;
q<=q1;
ENDfen;
(2)占空比可调
LIBRARYIEEE;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYPL_ASK1IS
PORT(CLK,START:
INSTD_LOGIC;
F:
OUTSTD_LOGIC);
ENDPL_ASK1;
ARCHITECTUREAOFPL_ASK1IS
SIGNALQ:
INTEGERRANGE0TO15;
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFSTART='0'THENQ<=0;F<='0';--------若不加F<='0',则当START='0'时,F赶到什么值就是什么
ELSIFQ<=2THENF<='1';Q<=Q+1;------改变“Q≤”后的值,可改变占空比;
ELSIFQ=15THENF<='0';Q<=0;-------改变Q后的值,可改变分频比
ELSEF<='0';Q<=Q+1;
ENDIF;
ENDIF;
ENDPROCESS;
ENDA;
六、变模计数器——交通灯控制系统
(1)模9减、模3减、模7减依次循环进行,更接近交通灯:
先红灯,再黄灯、再绿灯,再红、黄、绿。
。
。
东西与南北各一套变模计数器。
问题:
每次计数初始时多一个1111的状态,是时序问题
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitybianmo2is
port(clk,reset:
instd_logic;
q:
outstd_logic_vector(3downto0));
endbianmo2;
architecturebehaveofbianmo2is
typestatesis(st0,st1,st2,st3,st4,st5);
signals:
states;
signalq1:
std_logic_vector(3downto0);
begin
process(clk,reset)
begin
ifreset='1'then
s<=st0;
elsifclk'eventandclk='1'then
casesis
whenst0=>q1<="1001";s<=st1;
whenst1=>q1<=q1-1;ifq1="0000"thens<=st2;elses<=st1;endif;
whenst2=>q1<="0011";s<=st3;
whenst3=>q1<=q1-1;ifq1="0000"thens<=st4;elses<=st3;endif;
whenst4=>q1<="0111";s<=st5;
whenst5=>q1<=q1-1;ifq1="0000"thens<=st0;elses<=st5;endif;
endcase;
endif;
endprocess;
q<=q1;
endbehave;
注:
此状态机主控进程若为2个,则计数混乱,不受脉冲控制,因2进程的状态机的CASE语句因无CLK控制,所以此进程的计数为没有章法的
(2)
问题:
仿真时首次a=“00”时,状态不准,其余全部正确。
LibraryIEEE;
USEIEEE.std_logic_1164.all;
USEIEEE.std_logic_arith.all;
USEIEEE.std_logic_unsigned.all;
-----
EntityjsqIs
PORT(a:
bufferstd_logic_vector(1DOWNTO0);
cp:
instd_logic;
co:
bufferstd_logic;
QL,QH:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));
Endjsq;
-------
ArchitecturebehaviorofjsqIS
---signaln:
std_logic;
BEGIN
PROCESS(CP)
begin
---n<=a;
---------------
IF(CP'EVENTANDCP='1')THEN
IFa="00"then
IF(QH=2andQL=2)THENQH<="0000";QL<="0000";co<='1';
elsif(QL=9)THENQL<="0000";QH<=QH+1;co<='0';
elseQL<=QL+1;co<='0';
endif;
------------------------------------------------------------------------
elsifa="01"then
if(QH=1andQL=2)THENQH<="0000";QL<="0000";co<='1';
elsif(QL=9)THENQL<="0000";QH<=QH+1;co<='0';
elseQL<=QL+1;co<='0';
endif;
-------------------------------------------------------------------------
elsifa="10"then
if(QH=3andQL=2)THENQH<="0000";QL<="0000";co<='1';
elsif(QL=9)THENQL<="0000";QH<=QH+1;co<='0';
elseQL<=QL+1;co<='0';
endif;
-------------------------------------------------------------------------
elsifa="11"then
if(QH=4andQL=2)THENQH<="0000";QL<="0000";co<='1';
elsif(QL=9)THENQL<="0000";QH<=QH+1;co<='0';
elseQL<=QL+1;co<='0';
endif;
-------------------------------------------------------------------------------
endif;
endif;
ENDPROCESS;
---------------------
PROCESS
begin
waituntilQH<="0000"andQL<="0000";a<=
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