超大规模集成电路第八次作业秋段成华.docx
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超大规模集成电路第八次作业秋段成华.docx
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超大规模集成电路第八次作业秋段成华
Assignment8
1.Accessrelevantreferencebooksortechnicaldatabooksandgiveaccuratedefinitionsforthefollowingtimingparameters:
(1)designentity,
(2)signaldriver,
(3)transaction,
(4)event,
(5)timequeue,
(6)deltadelay,
(7)simulationtime,
(8)simulationcycle,
(9)inertialtime,
(10)transporttime.
(1)designentity:
InVHDLagivenlogiccircuitrepresentedasadesignentity.Adesignentity,inreturn,consistsoftwodifferenttypesofdescription:
theinterfacedescriptionandoneormorearchitecturalbodies.Theinterfacedescriptiondeclarestheentityanddescribesitsinputsandoutputs.
(2)signaldriver:
IfaprocesscontainsoneormoresignalassignmentstatementthatschedulefuturevaluesforsomesignalX,theVHDLsimulatorcreatesasinglevalueholdercalledasignaldriver.
(3)transaction:
Apairconsistingofavalueandtime.Thevaluepartrepresentsafuturevalueofthedriver;thetimepartrepresentsthetimeatwhichthevaluepartbecomesthecurrentvalueofdriver.
(4)event:
It’sakindofsignalpropertyandpresentssignaljump.Suchasif(clk'eventandclk='1).
(5)timequeue:
It’susedtokeepsomesignaltransactionsinthesimulator.Timequeueentriesarerepresentedasatwo-tupleoftheform(SN,V),whereSNisasignalnameandVisthevaluethesignalisscheduledtoassumeatthescheduledtime.Eachtimequeueentryiscalledasignaltransaction.
(6)deltadelay:
Aperiodoftimegreaterthan0,butlessthananystandardtimeunitnonumberofdeltadelayaddedtogethercancausesimulationtimetoadvance.
(7)simulationtime:
Theelapsedtimeinstandardtimeunitsduringsimulation.
(8)simulationcycle:
Everytimesimulationtimeadvances,asimulationcycleoccurs,whichwenowdefinemoreformally.Theexecutionofamodelconsistsofaninitializationphasefollowedbytherepetitiveexecutionofprocessesintheprocessnetwork.Eachrepetitionissaidtobeasimulationcycle.
(9)inertialtime:
Example:
Z<=Iafter10ns;ThesignalpropagationwilltakeplaceifandonlyifinputIpersistsatagivenlevelfor10ns-theamountoftimespecifiedintheafterclause.
(10)transporttime:
Z<=transportIafter10ns;AllchangesonIwillpropagatetoZ,regardlessofhowlongthevalueofIstaysatthenewlevel.
2.ConstructVHDLmodelsfor74-139dual2-to-4-linedecodersusingthreedescriptiontypes,i.e.,behavioral,dataflowandstructuraldescriptions.SynthesizeandsimulatethesemodelsrespectivelyintheenvironmentofXilinxISEwiththeModelSimsimulatorintegrated.Whensimulatingthesemodels,testvector(s)arerequiredtostimulatetheunitsundertest(UUT).ReasonabletestvectorsaredesignedandcreatedbyyourownassourcesaddedtoyourVHDLproject.
Logicschematicof74-139:
Functiontableofonedecoderof74-139:
INPUTS
OUTPUTS
ENABLE
SELECT
B
A
Y0
Y1
Y2
Y3
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
(1)、行为描述代码如下:
--Company:
--Engineer:
--CreateDate:
21:
14:
0912/02/2016
--DesignName:
--ModuleName:
deceoder_beh-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--Dependencies:
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitydeceoder_behis
Port(G1,G2:
instd_logic;
A:
instd_logic_vector(1downto0);
B:
instd_logic_vector(1downto0);
Y1:
outstd_logic_vector(3downto0);
Y2:
outstd_logic_vector(3downto0));
enddeceoder_beh;
architectureBehavioralofdeceoder_behis
begin
de1:
process(A,G1)
begin
ifG1='1'then
y1<="1111";--sequentialstatement
else
caseAis
when"00"=>Y1<="1110";
when"01"=>Y1<="1101";
when"10"=>Y1<="1011";
when"11"=>Y1<="0111";
whenothers=>Y1<="1111";
endcase;
endif;
endprocess;
de2:
process(B,G2)
begin
ifG2='1'then
Y2<="1111";--sequentialstatement
else
caseBis
when"00"=>Y2<="1110";
when"01"=>Y2<="1101";
when"10"=>Y2<="1011";
when"11"=>Y2<="0111";
whenothers=>Y2<="1111";
endcase;
endif;
endprocess;
endBehavioral;
TestBench代码如下:
--Company:
--Engineer:
--CreateDate:
22:
25:
5912/02/2016
--DesignName:
--ModuleName:
D:
/ISE11.1_example/decoder/deconder_beh_tb.vhd
--ProjectName:
decoder
--TargetDevice:
--Toolversions:
--Description:
--VHDLTestBenchCreatedbyISEformodule:
deceoder_beh
--Dependencies:
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--Notes:
--Thistestbenchhasbeenautomaticallygeneratedusingtypesstd_logicand
--std_logic_vectorfortheportsoftheunitundertest.Xilinxrecommends
--thatthesetypesalwaysbeusedforthetop-levelI/Oofadesigninorder
--toguaranteethatthetestbenchwillbindcorrectlytothepost-implementation
--simulationmodel.
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.all;
USEieee.numeric_std.ALL;
ENTITYdeconder_beh_tbIS
ENDdeconder_beh_tb;
ARCHITECTUREbehaviorOFdeconder_beh_tbIS
--ComponentDeclarationfortheUnitUnderTest(UUT)
COMPONENTdeceoder_beh
PORT(
G1:
INstd_logic;
G2:
INstd_logic;
A:
INstd_logic_vector(1downto0);
B:
INstd_logic_vector(1downto0);
Y1:
OUTstd_logic_vector(3downto0);
Y2:
OUTstd_logic_vector(3downto0)
);
ENDCOMPONENT;
--Inputs
signalG1:
std_logic:
='0';
signalG2:
std_logic:
='0';
signalA:
std_logic_vector(1downto0):
=(others=>'0');
signalB:
std_logic_vector(1downto0):
=(others=>'0');
--Outputs
signalY1:
std_logic_vector(3downto0);
signalY2:
std_logic_vector(3downto0);
BEGIN
--InstantiatetheUnitUnderTest(UUT)
uut:
deceoder_behPORTMAP(
G1=>G1,
G2=>G2,
A=>A,
B=>B,
Y1=>Y1,
Y2=>Y2
);
--Stimulusprocess
stim_proc:
process
begin
--insertstimulushere
G1<='1';
WAITFOR100ns;
G1<='0';
A<="00";
B<="00";
---------------------------------------
---------------CurrentTime:
200ns
WAITFOR100ns;
G1<='0';
A<="01";
B<="01";
---------------------------------------
---------------CurrentTime:
300ns
WAITFOR100ns;
G1<='0';
A<="10";
B<="10";
---------------------------------------
---------------CurrentTime:
400ns
WAITFOR100ns;
G1<='0';
a<="11";
b<="11";
WAITFOR100ns;
endprocess;
END;
测试波形如下:
可以看到当G1=0和G2=0可以正常的译码,当G1=1和G2=1,则Y1和Y2都输出”1111”。
(2)数据流代码如下:
--Company:
--Engineer:
--CreateDate:
23:
14:
3112/02/2016
--DesignName:
--ModuleName:
decoder_dataf-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitydecoder_datafis
Port(G1,G2:
instd_logic;
A:
instd_logic_vector(1downto0);
B:
instd_logic_vector(1downto0);
Y1:
outstd_logic_vector(3downto0);
Y2:
outstd_logic_vector(3downto0));
enddecoder_dataf;
architecturedataflowofdecoder_datafis
signalG11,G22:
std_logic;
signalA0,A1:
std_logic;
signalB0,B1:
std_logic;
begin
G11<=notG1;
G22<=notG2;
A0<=notA(0);
B0<=notB(0);
A1<=notA
(1);
B1<=notB
(1);
Y1(0)<=not(G11andA0andA1);
Y2(0)<=not(G22andB0andB1);
Y1
(1)<=not(G11andA1and(notA0));
Y2
(1)<=not(G22andB1and(notB0));
Y1
(2)<=not(G11andA0and(notA1));
Y2
(2)<=not(G22andB0and(notB1));
Y1(3)<=not(G11and(notA0)and(notA1));
Y2(3)<=not(G22and(notB0)and(notB1));
enddataflow;
TestBench代码没有改变。
可以看到与
(1)中结论一致得到如下波形。
(3)结构描述代码如下:
--Company:
--CreateDate:
12:
01:
2612/03/2016
--DesignName:
--ModuleName:
decoder_stuc-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--Dependencies:
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthiscode.
libraryUNISIM;
useUNISIM.VComponents.all;
entitydecoder_stucis
PORT(
G1:
INstd_logic;
G2:
INstd_logic;
A:
INstd_logic_vector(1downto0);
B:
INstd_logic_vector(1downto0);
Y1:
OUTstd_logic_vector(3downto0);
Y2:
OUTstd_logic_vector(3downto0)
);
enddecoder_stuc;
architecturestructofdecoder_stucis
signalG11,G22:
std_logic;
signalA0,A1:
std_logic;
signalB0,B1:
std_logic;
signalA00,A11:
std_logic;
signalB00,B11:
std_logic;
signalY11:
std_logic_vector(3downto0);
signalY22:
std_logic_vector(3downto0);
begin
U0:
INVportmap(A0,A(0));
U1:
INVportmap(B0,B(0));
U2:
INVportmap(G11,G1);
U3:
INVportmap(G22,G2);
U4:
INVportmap(A1,A
(1));
U5:
INVportmap(B1,B
(1));
U6:
INVportmap(A00,A0);
U7:
INVportmap(B00,B0);
U8:
INVportmap(A11,A1);
U9:
INVportmap(B11,B1);
U10:
nand3portmap(Y11(0),A0,A1,G11);
U11:
nand3portmap(Y22(0),B0,B1,G22);
U12:
nand3portmap(Y11
(1),G11,A1,A00);
U13:
nand3portmap(Y22
(1),G22,B1,B00);
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