函数信号发生器等vhdl程序.docx
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函数信号发生器等vhdl程序.docx
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函数信号发生器等vhdl程序
分频器:
--Copyright(C)1991-2008AlteraCorporation
--YouruseofAlteraCorporation'sdesigntools,logicfunctions
--andothersoftwareandtools,anditsAMPPpartnerlogic
--functions,andanyoutputfilesfromanyoftheforegoing
--(includingdeviceprogrammingorsimulationfiles),andany
--associateddocumentationorinformationareexpresslysubject
--tothetermsandconditionsoftheAlteraProgramLicense
--SubscriptionAgreement,AlteraMegaCoreFunctionLicense
--Agreement,orotherapplicablelicenseagreement,including,
--withoutlimitation,thatyouruseisforthesolepurposeof
--programminglogicdevicesmanufacturedbyAlteraandsoldby
--Alteraoritsauthorizeddistributors.Pleaserefertothe
--applicableagreementforfurtherdetails.
--PROGRAM"QuartusII"
--VERSION"Version8.1Build16310/28/2008SJFullVersion"
--CREATEDON"FriSep2322:
47:
562011"
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYfenpinIS
PORT
(
clk1:
INSTD_LOGIC;
clk:
OUTSTD_LOGIC
);
ENDfenpin;
ARCHITECTUREbdf_typeOFfenpinIS
ATTRIBUTEblack_box:
BOOLEAN;
nATTRIBUTEnoopt:
BOOLEAN;
COMPONENT\74163_0\
PORT(ENT:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ENP:
INSTD_LOGIC;
LDN:
INSTD_LOGIC;
RCO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74163_0\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74163_0\:
COMPONENTIStrue;
COMPONENT\74163_1\
PORT(ENT:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ENP:
INSTD_LOGIC;
LDN:
INSTD_LOGIC;
RCO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74163_1\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74163_1\:
COMPONENTIStrue;
COMPONENT\74163_2\
PORT(ENT:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ENP:
INSTD_LOGIC;
LDN:
INSTD_LOGIC;
RCO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74163_2\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74163_2\:
COMPONENTIStrue;
COMPONENT\74163_3\
PORT(ENT:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ENP:
INSTD_LOGIC;
LDN:
INSTD_LOGIC;
RCO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74163_3\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74163_3\:
COMPONENTIStrue;
COMPONENT\74163_4\
PORT(ENT:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
ENP:
INSTD_LOGIC;
LDN:
INSTD_LOGIC;
RCO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74163_4\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74163_4\:
COMPONENTIStrue;
SIGNALSYNTHESIZED_WIRE_24:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_6:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_11:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_16:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_21:
STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_24<='1';
b2v_inst:
74163_0
PORTMAP(ENT=>SYNTHESIZED_WIRE_24,
CLRN=>SYNTHESIZED_WIRE_24,
CLK=>clk1,
ENP=>SYNTHESIZED_WIRE_24,
LDN=>SYNTHESIZED_WIRE_24,
RCO=>SYNTHESIZED_WIRE_6);
b2v_inst1:
74163_1
PORTMAP(ENT=>SYNTHESIZED_WIRE_24,
CLRN=>SYNTHESIZED_WIRE_24,
CLK=>SYNTHESIZED_WIRE_6,
ENP=>SYNTHESIZED_WIRE_24,
LDN=>SYNTHESIZED_WIRE_24,
RCO=>SYNTHESIZED_WIRE_11);
b2v_inst2:
74163_2
PORTMAP(ENT=>SYNTHESIZED_WIRE_24,
CLRN=>SYNTHESIZED_WIRE_24,
CLK=>SYNTHESIZED_WIRE_11,
ENP=>SYNTHESIZED_WIRE_24,
LDN=>SYNTHESIZED_WIRE_24,
RCO=>SYNTHESIZED_WIRE_16);
b2v_inst3:
74163_3
PORTMAP(ENT=>SYNTHESIZED_WIRE_24,
CLRN=>SYNTHESIZED_WIRE_24,
CLK=>SYNTHESIZED_WIRE_16,
ENP=>SYNTHESIZED_WIRE_24,
LDN=>SYNTHESIZED_WIRE_24,
RCO=>SYNTHESIZED_WIRE_21);
b2v_inst5:
74163_4
PORTMAP(ENT=>SYNTHESIZED_WIRE_24,
CLRN=>SYNTHESIZED_WIRE_24,
CLK=>SYNTHESIZED_WIRE_21,
ENP=>SYNTHESIZED_WIRE_24,
LDN=>SYNTHESIZED_WIRE_24,
RCO=>clk);
ENDbdf_type;
序列信号发生器
-LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYfashengqiIS
PORT
(
pin_name:
INSTD_LOGIC;
xulie:
OUTSTD_LOGIC
);
ENDfashengqi;
ARCHITECTUREbdf_typeOFfashengqiIS
ATTRIBUTEblack_box:
BOOLEAN;
nATTRIBUTEnoopt:
BOOLEAN;
COMPONENT\74175_0\
PORT(D1:
INSTD_LOGIC;
D2:
INSTD_LOGIC;
D3:
INSTD_LOGIC;
D4:
INSTD_LOGIC;
Q1:
OUTSTD_LOGIC;
QN1:
OUTSTD_LOGIC;
Q2:
OUTSTD_LOGIC;
QN2:
OUTSTD_LOGIC;
Q3:
OUTSTD_LOGIC;
QN3:
OUTSTD_LOGIC;
Q4:
OUTSTD_LOGIC;
QN4:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74175_0\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74175_0\:
COMPONENTIStrue;
SIGNALSYNTHESIZED_WIRE_15:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_16:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_2:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_3:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_4:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_5:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_7:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_8:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_9:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_10:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_11:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_12:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_13:
STD_LOGIC;
BEGIN
xulie<=SYNTHESIZED_WIRE_3;
SYNTHESIZED_WIRE_7<=SYNTHESIZED_WIRE_15ANDSYNTHESIZED_WIRE_16;
SYNTHESIZED_WIRE_9<=SYNTHESIZED_WIRE_2ANDSYNTHESIZED_WIRE_3;
SYNTHESIZED_WIRE_8<=SYNTHESIZED_WIRE_4ANDSYNTHESIZED_WIRE_5ANDSYNTHESIZED_WIRE_16;
SYNTHESIZED_WIRE_10<=SYNTHESIZED_WIRE_7ORSYNTHESIZED_WIRE_8;
SYNTHESIZED_WIRE_11<=SYNTHESIZED_WIRE_9ORSYNTHESIZED_WIRE_10;
b2v_inst8:
74175_0
PORTMAP(D1=>SYNTHESIZED_WIRE_11,
D2=>SYNTHESIZED_WIRE_12,
D3=>SYNTHESIZED_WIRE_13,
D4=>SYNTHESIZED_WIRE_15,
Q1=>SYNTHESIZED_WIRE_12,
QN1=>SYNTHESIZED_WIRE_4,
Q2=>SYNTHESIZED_WIRE_13,
QN2=>SYNTHESIZED_WIRE_5,
Q3=>SYNTHESIZED_WIRE_15,
QN3=>SYNTHESIZED_WIRE_2,
Q4=>SYNTHESIZED_WIRE_3,
QN4=>SYNTHESIZED_WIRE_16);
ENDbdf_type;
串并转换:
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYchuanbingzhuanhuanIS
PORT
(
pin_name2:
INSTD_LOGIC;
a:
OUTSTD_LOGIC;
b:
OUTSTD_LOGIC;
c:
OUTSTD_LOGIC;
d:
OUTSTD_LOGIC;
e:
OUTSTD_LOGIC;
f:
OUTSTD_LOGIC;
g:
OUTSTD_LOGIC
);
ENDchuanbingzhuanhuan;
ARCHITECTUREbdf_typeOFchuanbingzhuanhuanIS
ATTRIBUTEblack_box:
BOOLEAN;
nATTRIBUTEnoopt:
BOOLEAN;
COMPONENT\74194_0\
PORT(SRSI:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
S1:
INSTD_LOGIC;
S0:
INSTD_LOGIC;
QA:
OUTSTD_LOGIC;
QB:
OUTSTD_LOGIC;
QC:
OUTSTD_LOGIC;
QD:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74194_0\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74194_0\:
COMPONENTIStrue;
COMPONENT\74194_1\
PORT(SRSI:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
CLRN:
INSTD_LOGIC;
S1:
INSTD_LOGIC;
S0:
INSTD_LOGIC;
QA:
OUTSTD_LOGIC;
QB:
OUTSTD_LOGIC;
QC:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\74194_1\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\74194_1\:
COMPONENTIStrue;
COMPONENTfashengqi
PORT(pin_name:
INSTD_LOGIC;
xulie:
OUTSTD_LOGIC
);
ENDCOMPONENT;
SIGNALSYNTHESIZED_WIRE_0:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_8:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_9:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_4:
STD_LOGIC;
BEGIN
d<=SYNTHESIZED_WIRE_4;
SYNTHESIZED_WIRE_8<='1';
SYNTHESIZED_WIRE_9<='0';
b2v_inst:
74194_0
PORTMAP(SRSI=>SYNTHESIZED_WIRE_0,
CLK=>pin_name2,
CLRN=>SYNTHESIZED_WIRE_8,
S1=>SYNTHESIZED_WIRE_9,
S0=>SYNTHESIZED_WIRE_8,
QA=>g,
QB=>f,
QC=>e,
QD=>SYNTHESIZED_WIRE_4);
b2v_inst1:
74194_1
PORTMAP(SRSI=>SYNTHESIZED_WIRE_4,
CLK=>pin_name2,
CLRN=>SYNTHESIZED_WIRE_8,
S1=>SYNTHESIZED_WIRE_9,
S0=>SYNTHESIZED_WIRE_8,
QA=>c,
QB=>b,
QC=>a);
b2v_inst2:
fashengqi
PORTMAP(pin_name=>pin_name2,
xulie=>SYNTHESIZED_WIRE_0);
ENDbdf_type;
串行检测:
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYchuanxingjianceIS
PORT
(
b:
INSTD_LOGIC;
c:
INSTD_LOGIC;
a:
OUTSTD_LOGIC
);
ENDchuanxingjiance;
ARCHITECTUREbdf_typeOFchuanxingjianceIS
BEGIN
a<=bORc;
ENDbdf_type;
并行检测:
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYbingxingjianceIS
PORT
(
pin_name:
INSTD_LOGIC;
tongbu:
OUTSTD_LOGIC
);
ENDbingxingjiance;
ARCHITECTUREbdf_typeOFbingxingjianceIS
ATTRIBUTEblack_box:
BOOLEAN;
nATTRIBUTEnoopt:
BOOLEAN;
COMPONENT\7485_0\
PORT(A3:
INSTD_LOGIC;
B2:
INSTD_LOGIC;
A2:
INSTD_LOGIC;
AEBI:
INSTD_LOGIC;
AGBI:
INSTD_LOGIC;
ALBI:
INSTD_LOGIC;
A0:
INSTD_LOGIC;
B0:
INSTD_LOGIC;
B3:
INSTD_LOGIC;
A1:
INSTD_LOGIC;
B1:
INSTD_LOGIC;
AEBO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\7485_0\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\7485_0\:
COMPONENTIStrue;
COMPONENT\7485_1\
PORT(A3:
INSTD_LOGIC;
B2:
INSTD_LOGIC;
A2:
INSTD_LOGIC;
AEBI:
INSTD_LOGIC;
AGBI:
INSTD_LOGIC;
ALBI:
INSTD_LOGIC;
A0:
INSTD_LOGIC;
B0:
INSTD_LOGIC;
B3:
INSTD_LOGIC;
A1:
INSTD_LOGIC;
B1:
INSTD_LOGIC;
ALBO:
OUTSTD_LOGIC;
AGBO:
OUTSTD_LOGIC;
AEBO:
OUTSTD_LOGIC);
ENDCOMPONENT;
ATTRIBUTEblack_boxOF\7485_1\:
COMPONENTIStrue;
ATTRIBUTEnooptOF\7485_1\:
COMPONENTIStrue;
COMPONENTchuanbingzhuanhuan
PORT(pin_name2:
INSTD_LOGIC;
g:
OUTSTD_LOGIC;
f:
OUTSTD_LOGIC;
e:
OUTSTD_LOGIC;
d:
OUTSTD_LOGIC;
c:
OUTSTD_LOGIC;
b:
OUTSTD_LOGIC;
a:
OUTSTD_LOGIC
);
ENDCOMPONENT;
SIGNALSYNTHESIZED_WIRE_0:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_22:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_2:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_3:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_4:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_5:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_6:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_23:
STD_LOGIC;
SIGNAL
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