Logic device Design Flow and Methodology.docx
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Logic device Design Flow and Methodology.docx
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LogicdeviceDesignFlowandMethodology
DesignFlowandMethodology
Introduction
ModernFieldProgrammableGateArray(FPGA)andComplexProgrammableLogicDevice(CPLD)chipswitheverincreasingsizesandspeedsallowdesignerstodeveloplarge,high-speeddigitalsystemsforaspecificapplicationveryquickly.Moderndesignflowsthatallowthedesignofportionsofthesysteminthemostnaturalrepresentationandsupportvirtualprototyping1mustbedevelopedtomanagecomplexityandexploitthisincreasingcapacity.ThesedesignflowsmustutilizethecapabilitiesofHardwareDescriptionLanguages,synthesis,andcosimulationtoachievethesegoals.
HardwareDescriptionLanguages(HDL)suchasVerilogandVHDLhavebeendevelopedthatallowthedescriptionofthebehaviorandthestructureofadigitalsysteminareadableandsimulatableform.Synthesistoolshavebeendevelopedthatcanderiveagate-levelhardwareimplementationofadigitalsystemfromabehavioraldescriptioninanHDL.ThesesynthesistoolstypicallyoperateatafairlylowlevelandarecapableofsynthesizingefficientFiniteStateMachine(FSM)implementationsorblocksofcombinationallogicfrombehavioralHDLdescriptions.SomesynthesistoolshavebeendevelopedthatoperateonmorecomplexHDLdescriptionsandperformRTL(registertransferlevel)datapathdesign,andschedulingandassignmentoperations,butthesetoolsgenerallyperformbestondataflowintensiveapplicationslikeDigitalSignalProcessingcomputations.Formorecontrolflowintensivesystemssuchasmicroprocessorsormicrocontrollers,orapplicationsthatrequirethemostefficientuseofhardwareresourcesandhavecriticaltimingrequirements,theRTLleveldatapathmustbedesignedbyhand.Themostefficientmethodfordesigningstructureistheuseoftraditionalschematiccapture.
ThisdocumentpresentsadesignflowfordevelopingActelFPGAsusingtheMentorGraphicsandActeltoolsets.BehavioralHDLdescriptions,logiclevelsynthesis,schematiccapture,andgraphicalHDLgenerationtechniquesareusedwheremostappropriatetoenablefast,efficientdesignofcomplexdigitalsystems.Extensivesimulationofvirtualprototypesisperformedateachstageinthedesignprocesstoverifythedesignaseachstepiscompleted.AlthoughtheexamplepresentedhereinusesVHDLastheHDLofchoice,allofthetoolsusedsupportVerilogandthusitcouldeasilybeusedinthisdesignflow.
Thenextsectionwillpresentanoverviewofthedesignflowandthefollowingsectionwillillustratethedesignflowinmoredetailusinganexample.
MGC/ActelDesignFlow
ThedesignflowdescribedinthisdocumentconsistsoffivemajorproceduresasshowninFigure1,FunctionalDesign,Synthesis,Place&Route,SystemIntegration,andFabrication.Althoughthedesignflowisdrawnasawaterfalldiagram,withflowonlyinadownwarddirection,itisinfactaniterativeprocessinwhichthedesignercanreturntoorredoanystepuntiltheproperfunctionalityisarrivedat.Withineachstep,withtheexceptionoftheFabricationprocess,thereisacompletegenerate-simulatecycleinwhichthedesigncomponentsaredevelopedandthensimulatedtoensurecorrectfunctionalitybeforemovingontothenextstep.Eachoftheseprocesseswillbedescribedinmoredetailinthefollowingsections.
FunctionalDesign
Functionaldesignistheprocessoftranslatingtheinitialsystemconceptintoanactualimplementationthatperformstherequiredfunctions.Inthecaseofthedesignflowdescribedhere,theinitialconceptmustincludehowthedesignistobepartitionedacrossseparateFPGAsifnecessary,asthetoolswillnotperformthepartitioningfunctionautomatically(someFPGAtoolswilldothis).AlsonotethattheActelfamilyofFPGAsdonotallowtri-statebusesinternaltotheFPGAalthoughtri-statepinsareavailableattheindividualFPGAboundaries.Therefore,theinternaldatapathofthedesignmustbebasedonmultiplexors,notbusses.
Functionaldesignbeginswiththedevelopmentofadescriptionofportions(buildingblocks)ofthesysteminthemostnaturalmethodpossibleforthecomponentinquestion.ForsimplestructuresbuiltfromActelprimitives,suchasmulti-bitregistersandmultiplexors,thesimplestdescriptionmechanismisschematiccaptureusingDesignArchitect(DA).ForblocksofrandomlogicsuchasdecodersorALUs,thesimplestdescriptionisoftenasynthesizableVHDLmodel-usuallygeneratedbyhand.ForFiniteStateMachines(FSMs)suchasareusedforcontrollers,etc.,thesimplestdescriptionisalsoasynthesizableVHDLmodel,butautomaticHDLgenerationtoolssuchasRenoircanbeusedtogeneratetheVHDLmodelfromanaturalgraphicaldescription.Aftertheinitialdescriptionofthebuildingblocksarecreated,theyshouldbesimulatedindividuallytoensurethattheyarefunctionallycorrect.Thisisdoneusingthesimulatorappropriateforthemodel,Quicksimforschematics,orModelSimforVHDLmodels.TheflowsforcreationandsimulationofthebuildingblocksareshowninFigure2.NotethattheActelpresimvpttoolmustbeusedtoprepareaunitdelaysimulationviewpointfortheschematicscreatedwithpartsfromtheActellibrarybeforeitcanbesimulatedwithQuicksim.
Oncetheindividualbuildingblocksaredesignedandsimulated,thenextstepisconstructionoftheRTLleveldatapathusingthebuildingblockspreviouslycreated.SincetheRTLleveldatapathisastructuralinterconnectionofbuildingblocksandpossiblysomeadditionalpartsfromtheActellibrary,thisstepismostefficientlyperformedusingschematiccapture,again,withDesignArchitect.BeforethebuildingblockscanbeinstantiatedinaDesignArchitectschematic,symbolsmustbecreatedforthem.ThisiseasilydoneforboththeschematicandVHDLbuildingblocksusingDesignArchitect.Afterthesymbolsarecreated,DesignArchitectcanbeusedtocreatetheoverallstructureofthedesignbyinterconnectingthebuildingblocksinaschematic.Oncethisstepiscomplete,theentiredesignshouldbefunctionallysimulatedagaintoensurecorrectoperation.Notesimulationscanbeperformediterativelyastheschematicisbuiltup,whichhelpstoisolateproblemsastheyappear.Forexample,itmaybehelpfultosimulatethedatapathbyitselfwithoutthecontrollerfirst,usingsimulatorforcefilestodrivethecontrolpointstoinsureitoperatescorrectly.Thenthecontrollermodelcanbeaddedandtheresultingdesignsimulated.Finally,theI/Opadsandanyadditionallogic,suchasresetgeneratorsorgluelogic,canbeaddedandtheentiredesign(usuallyacompleteFPGA)canbesimulated.
IncreatingthesymbolsfortheVHDLmodels,DesignArchitectwillautomaticallyaddallofthepropertiesnecessarytousetheFlexsimbackplanetocosimulatethemwithQuicksimparts.FlexsimisthesimulationbackplanethatconnectstheQuicksimandModelSimsimulatorstogetherandisinvokedusingtheQSProtool.ThereiscaveatwhenusingtheQSProtooltocosimulateQuicksimpartswithVHDLmodels;thecombinationdoesnothandlezerodelaysimulationsverywell.Ataminimum,ifyoudonotadddelaystothecontroloutputsoftheFSMVHDLmodel,itwillbeverydifficulttodeterminetheorderofeventsafteraclockcycle.Intheworstcase,thesimulationwillnotfunctioncorrectlyastheeventsinzerotimedonotseemtomaintainproperorder(acompleteVHDLsimulationwouldnothavethisproblemasVHDL'sdeltadelaymechanismwasspecificallydesignedtohandleit).AneasysolutionistoaddafewnanoseconddelaytotheassignmentoftheoutputsinallVHDLmodels.ThisiseasilydoneinthebehavioralVHDLmodelsthatarewrittenbyhandorinthemodelsgeneratedbyRenoir.Duringthesynthesisprocess,thesedelayswillbeignored,buttheymakethefunctionalsimulationprocessmucheasier.Figure3showsthedesignflowforfunctionaldesignattheRTLlevel.
Synthesis
SynthesisistheprocessofmappingtheVHDLbehavioralmodelsintologicgateimplementations.Inthisdesignflow,synthesisisperformedusingtheLeonardoSpectrumtoolfromExemplarthatispartoftheMentorGraphicstoolset.LeonardoSpectrumisasynthesistoolwhichcantargetFPGAimplementations.ItacceptseitherVHDLorVerilogasitsinputandgeneratesandoutputwhichconsistsnetlistoflibrarypartsinthechosentechnology,inthiscasetheActelACT1family.TheoutputnetlistformatcanbeeitherEDIF(ElectronicDesignInterchangeFormat)VHDL,Verilog,orXNF(anetlistformatspecificallyforXilinxFPGAtools).Forthisdesignflow,theEDIFoutputformatwillbeusedasthisiseasilyimportedbackintotheMentorGraphicsenvironment.
Oneofthekeystothesynthesisprocess,ofcourse,istowritesynthesizableVHDLmodelsinthebeginning,aspartofthefunctionaldesignprocess.BecauseVHDLisahighlevellanguage,itcontainsanumberofcomplexconstructsandallowsmodelinginvariousstyles(suchasrecursion)whicharemeaninglessintermsofanactualhardwareimplementation,andthereforearenotsynthesizable.Fortunately,theRenoirtoolgeneratessynthesizablecodeforstatemachines,soallthatisnecessaryistoensurethatthebehavioraldescriptionsthatarewrittenbyhandfortherandomlogicblocksaresynthesizable.MostsimplebehavioralVHDLdescriptionsareinfactsynthesizable,butthereareanumberofbooksandreferencesonwritingsynthesizableVHDLincludingtheHDLSynthesisGuidethatdescribestheVHDLsubsetandcodingstylethattheLeonardoSpectrumtoolaccepts.ThisreferenceshouldbeconsultedifanyquestionsonthesynthesizabilityofaVHDLmodelbyLeonardoSpectrumarise.
OncetheVHDLcodeissynthesizedintoagatelevelimplement
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