vhdl语言例程集锦.docx
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vhdl语言例程集锦.docx
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vhdl语言例程集锦
vhdl语言例程集锦
ExamplesofVHDLDescriptions
AdvancedElectronicDesignAutomation
ExamplesofVHDLDescriptions
Author:
IanElliottofNorthumbriaUniversity
ThisfilecontainsaselectionofVHDLsourcefileswhichservetoillustratethediversityandpowerofthelanguagewhenusedtodescribevarioustypesofhardware.Theexamplesrangefromsimplecombinationallogic,describedin
termsofbasiclogicgates,tomorecomplexsystems,suchasabehaviouralmodelofamicroprocessorandassociatedmemory.AlloftheexamplescanbesimulatedusinganyIEEEcompliantVHDLsimulatorandmanycanbe
synthesisedusingcurrentsynthesistools.
Usethehierarchicallinksbelowtonavigateyourwaythroughtheexamples:
lCombinationalLogic
lCounters
lShiftRegisters
lMemory
lStateMachines
lRegisters
lSystems
lADCandDAC
lArithmetic
CombinationalLogic
lExclusive-ORGate(Dataflowstyle)
lExclusive-ORGate(Behaviouralstyle)
lExclusive-ORGate(Structuralstyle)
lMiscellaneousLogicGates
lThree-inputMajorityVoter
lMagnitudeComparator
lQuad2-inputNand(74x00)
lBCDtoSevenSegmentDecoder
lDual2-to-4Decoder
lOctalBusTransceiver
lQuad2-inputOR
l8-bitIdentityComparator
lHammingEncoder
lHammingDecoder
l2-to-4DecoderwithTestbenchandConfiguration
lMultiplexer16-to-4usingSelectedSignalAssignmentStatement
lMultiplexer16-to-4usingConditionalSignalAssignmentStatement
lMultiplexer16-to-4usingif-then-elsif-elseStatement
lM68008AddressDecoder
lHighestPriorityEncoder
lN-inputANDGate
Counters
http:
//www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdl
exmp.html(1of67)[23/1/20024:
15:
01]
ExamplesofVHDLDescriptions
lCounterusingaConversionFunction
lGeneratedBinaryUpCounter
lCounterusingMultipleWaitStatements
lSynchronousDownCounterwithParallelLoad
lMod-16CounterusingJKFlip-flops
lPseudoRandomBitSequenceGenerator
lUniversalCounter/Register
ln-BitSynchronousCounter
ShiftRegisters
lUniversalShiftRegister/Counter
lTTL164ShiftRegister
lBehaviouraldescriptionofan8-bitShiftRegister
lStructuralDescriptionofan8-bitShiftRegister
Memory
lROM-basedWaveformGenerator
lAFirst-inFirst-outMemory
lBehaviouralmodelofa16-word,8-bitRandomAccessMemory
lBehaviouralmodelofa256-word,8-bitReadOnlyMemory
StateMachines
lClassic2-ProcessStateMachineandTestBench
lStateMachineusingVariable
lStateMachinewithAsynchronousReset
lPatternDetectorFSMwithTestBench
lStateMachinewithMooreandMealyoutputs
lMooreStateMachinewithExplicitStateencoding
lMealyStateMachinewithRegisteredOutputs
lMooreStateMachinewithConcurrentOutputLogic
Systems
lPelicanCrossingController
lSimpleMicroprocessorSystem
lBoothMultiplier
lLotteryNumberGenerator
lDigitalDelayUnit
lChessClock
ADCandDAC
lPackagedefiningaBasicAnaloguetype
l16-bitAnaloguetoDigitalConverter
l16-bitDigitaltoAnalogueConverter
l8-bitAnaloguetoDigitalConverter
l8-bitUnipolarSuccessiveApproximationADC
http:
//www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html(2of67)[23/1/20024:
15:
07]
ExamplesofVHDLDescriptions
Arithmetic
l8-bitUnsignedMultiplier
ln-bitAdderusingtheGenerateStatement
lAVarietyofAdderStyles
lBoothMultiplier
Registers
lUniversalRegister
lOctalD-TypeRegisterwith3-StateOutputs
lQuadD-TypeFlip-flop
l8-bitRegisterwithSynchronousLoadandClear
UniversalRegister
Description-Thisdesignisauniversalregisterwhichcanbeusedasastraightforwardstorageregister,abi-directionalshiftregister,anupcounterandadowncounter.Theregistercanbeloadedfromasetofparalleldatainputs
andthemodeiscontrolledbya3-bitinput.The'termcnt'(terminalcount)outputgoeshighwhentheregistercontainszero.
LIBRARYieee;
USE
USE
ENTITYunicntrIS
GENERIC(n:
Positive:
=8);--sizeofcounter/shifter
PORT(clock,serinl,serinr:
INStd_logic;--serialinputsmode:
INStd_logic_vector(2DOWNTO0);--modecontroldatain:
INStd_logic_vector((n-1)DOWNTO0);--parallelinputsdataout:
OUTStd_logic_vector((n-1)DOWNTO0);--paralleloutputstermcnt:
OUTStd_logic);--terminalcountoutputENDunicntr;
ARCHITECTUREv1OFunicntrIS
SIGNALint_reg:
Std_logic_vector((n-1)DOWNTO0);
BEGIN
main_proc:
PROCESS
BEGIN
WAITUNTILrising_edge(clock);
CASEmodeIS
--reset
WHEN"000"=>int_reg<=(OTHERS=>'0');
--parallelload
WHEN"001"=>int_reg<=datain;
--countup
WHEN"010"=>int_reg<=int_reg+1;
--countdown
WHEN"011"=>int_reg<=int_reg-1;
--shiftleft
WHEN"100"=>int_reg<=int_reg((n-2)DOWNTO0)&serinl;
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