一篇关于FPGA的英文文献及翻译.docx

一篇关于FPGA的英文文献及翻译.docx

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一篇关于FPGA的英文文献及翻译

使用LabVIEWFPGA模块开发可编程自动化控制器

学院：

通信与电子工程学院

班级：

电子071

学号：

2007131010

姓名：

欧洪材

BuildingProgrammableAutomationControllerswithLabVIEWFPGA

Overview

ProgrammableAutomationControllers（PACs）aregainingacceptancewithintheindustrialcontrolmarketastheidealsolutionforapplicationsthatrequirehighlyintegratedanaloganddigitalI/O,floating-pointprocessing,andseamlessconnectivitytomultipleprocessingnodes.NationalInstrumentsoffersavarietyofPACsolutionspoweredbyonecommonsoftwaredevelopmentenvironment,NILabVIEW.WithLabVIEW,youcanbuildcustomI/Ointerfacesforindustrialapplicationsusingadd-onsoftware,suchastheNILabVIEWFPGAModule.

WiththeLabVIEWFPGAModuleandreconfigurableI/O（RIO）hardware,NationalInstrumentsdeliversanintuitive,accessiblesolutionforincorporatingtheflexibilityandcustomizabilityofFPGAtechnologyintoindustrialPACsystems.YoucandefinethelogicembeddedinFPGAchipsacrossthefamilyofRIOhardwaretargetswithoutknowinglow-levelhardwaredescriptionlanguages（HDLs）orboard-levelhardwaredesigndetails,aswellasquicklydefinehardwareforultrahigh-speedcontrol,customizedtimingandsynchronization,low-levelsignalprocessing,andcustomI/Owithanalog,digital,andcounterswithinasingledevice.YoualsocanintegrateyourcustomNIRIOhardwarewithimageacquisitionandanalysis,motioncontrol,andindustrialprotocols,suchasCANandRS232,torapidlyprototypeandimplementacompletePACsystem.

TableofContents

1.Introduction

2.NIRIOHardwareforPACs

3.BuildingPACswithLabVIEWandtheLabVIEWFPGAModule

4.FPGADevelopmentFlow

5.UsingNISoftMotiontoCreateCustomMotionControllers

6.Applications

7.Conclusion

Introduction

YoucanusegraphicalprogramminginLabVIEWandtheLabVIEWFPGAModuletoconfiguretheFPGA（field-programmablegatearray）onNIRIOdevices.RIOtechnology,themergingofLabVIEWgraphicalprogrammingwithFPGAsonNIRIOhardware,providesaflexibleplatformforcreatingsophisticatedmeasurementandcontrolsystemsthatyoucouldpreviouslycreateonlywithcustom-designedhardware.

AnFPGAisachipthatconsistsofmanyunconfiguredlogicgates.Unlikethefixed,vendor-definedfunctionalityofanASIC（application-specificintegratedcircuit）chip,youcanconfigureandreconfigurethelogiconFPGAsforyourspecificapplication.FPGAsareusedinapplicationswhereeitherthecostofdevelopingandfabricatinganASICisprohibitive,orthehardwaremustbereconfiguredafterbeingplacedintoservice.Theflexible,software-programmablearchitectureofFPGAsofferbenefitssuchashigh-performanceexecutionofcustomalgorithms,precisetimingandsynchronization,rapiddecisionmaking,andsimultaneousexecutionofparalleltasks.Today,FPGAsappearinsuchdevicesasinstruments,consumerelectronics,automobiles,aircraft,copymachines,andapplication-specificcomputerhardware.WhileFPGAsareoftenusedinindustrialcontrolproducts,FPGAfunctionalityhasnotpreviouslybeenmadeaccessibletoindustrialcontrolengineers.DefiningFPGAshashistoricallyrequiredexpertiseusingHDLprogrammingorcomplexdesigntoolsusedmorebyhardwaredesignengineersthanbycontrolengineers.Within the test-fixture the tx output of the transmitter module is looped back to the rx input of the receiver module. This allows the transmitter module to be used as test signal generator for the receiver module. Data can be written in parallel format to the transmitter module and looped back in serial format to the rx input of the receiver module, and data received can finally be read out in parallel format from the receiver module. In order to automate the testing of the UART as much as possible, tree independent Verilog tasks were written as follows. The Verilog task“write_to_transmitter” holds all necessary statements required to generate a single parallel data write sequence to the transmitter module. Data that are written to the transmitter upon execution of the “write_to_transmitter” task, get latched internal to the test-fixture for later analysis. The Verilog task “read_out_receiver” holds all necessary statements required to generate a single parallel data read out sequence from the receiver module. Data that are read out of the receiver upon execution of the “read_out_receiver” task, get latched internal to the test-fixture for later analysis. The Verilog task “compare_data” holds all necessary statements required to compare the previous data written to the transmitter module, to the corresponding and most recent data received and read out from the receive r module. If any discrepancy occurs, the “compare_data” task flags for an error by writing out the data values that were written to the transmitter module, as well as the corresponding data values that were received by and read out from the receiver module. The simulation is immediately stopped by the “compare_data” task if any discrepancy occurs. Besides the tree above mentioned Verilog tasks, the test-fixture holds the statements to generate the mclkx16, the master reset signals as well as the “tx to rx” loop back feature. The statements are considered trivial, and will not be illustrated here, but can be referred to within the test-fixture itself. The core of the test-fixture is a behavioral level “for loop” that executes the tree above mentioned Verilog tasks in order to write all possible data combinations to the transmitter and verify that same data gets properly received by the receiver. The for loop is showedbelowinfigure21.Next to port definitions comes port directions. Directions are specified as input, output or inout （bidirectional）, and can be referred to in table 1. Next to the specification of port directions comes declaration of internal signals. Internal signals in Verilog are declared as “wire” or “reg” data types. Signals of the “wire” type are used for continuos assignments, also called combinatorial statements. Signals of the “reg” type are used for assignments within the Verilog “always” block, often use for sequential logic assignments, but not necessarily. For further explanation see aVerilog reference book. Data types of the internal signals of the module can be referred to in table 3.We have now passed by all necessary declarations, and are now ready to look at the actual implementation. Using hardware description language allows us to describe the function of the transmitter in a more behavioral manner, rather than focus on it’s actual implementation at gate level In software programming language, functions and procedures breaks larger programs into more readable, manageable and certainly maintainable pieces. The Verilog language provides functions and tasks as constructs, analogous to software functions and procedures. A Verilog function and task are used as the equivalent to multiple lines of Verilog code, where certain inputs or signals affects certain outputs or variables. The use of functions and tasks usually takes place where multiple lines of code are repeatedly used in a design, and hence makes the design easier to read and certainly maintain. A Verilog function can have multiple inputs, but always have only one output, while the Verilog task can have both multiple inputs, and multiple outputs and even in some cases, non of each. Below is shown the Verilog task, that hold all necessary sequential statements, to describe the transmitter in the “shift” mode

WiththeLabVIEWFPGAModuleandNIRIOhardware,younowcanuseLabVIEW,ahigh-levelgraphicaldevelopmentenvironmentdesignedspecificallyformeasurementandcontrolapplications,tocreatePACsthathavethecustomization,flexibility,andhigh-performanceofFPGAs.BecausetheLabVIEWFPGAModuleconfigurescustomcircuitryinhardware,yoursystemcanprocessandgeneratesynchronizedanaloganddigitalsignalsrapidlyanddeterministically.Figure1illustratesmanyoftheNIRIOdevicesthatyoucanconfigureusingtheLabVIEWFPGAModule.

Figure1.LabVIEWFPGAVIBlockDiagramandRIOHardwarePlatforms

NIRIOHardwareforPACs

Historically,programmingFPGAshasbeenlimitedtoengineerswhohavein-depthknowledgeofVHDLorotherlow-leveldesigntools,whichrequireovercomingaverysteeplearningcurve.WiththeLabVIEWFPGAModule,NIhasopenedFPGAtechnologytoabroadersetofengineerswhocannowdefineFPGAlogicusingLabVIEWgraphicaldevelopment.Measurementandcontrolengineerscanfocusprimarilyontheirtestandcontrolapplication,wheretheirexpertiselies,ratherthanthelow-levelsemanticsoftransferringlogicintothecellsofthechip.TheLabVIEWFPGAModulemodelworksbecauseofthetightintegrationbetweentheLabVIEWFPGAModuleandthecommercialoff-the-shelf（COTS）hardwarearchitectureoftheFPGAandsurroundingI/Ocomponents.

NationalInstrumentsPACsprovidemodular,off-the-shelfplatformsforyourindustrialcontrolapplications.WiththeimplementationofRIOtechnologyonPCI,PXI,andCompactVisionSystemplatformsandtheintroductionofRIO-basedCompactRIO,engineersnowhavethebenefitsofaCOTSplatformwiththehigh-performance,flexibility,andcustomizationbenefitsofFPGAsattheirdisposaltobuildPACs.NationalInstrumentsPCIandPXIRSeriesplug-indevicesprovideanaloganddigitaldataacquisitionandcontrolforhigh-performance,user-configurabletimingandsynchronization,aswellasonboarddecisionmakingonasingledevice.Usingtheseoff-the-shelfdevices,youcanextendyourNIPXIorPCIindustrialcontrolsystemtoincludehigh-speeddiscreteandanalogcontrol,customsensorinterfaces,andprecisetimingandcontrol.

NICompactRIO,aplatformcenteredonRIOtechnology,providesasmall,industriallyrugged,modularPACplatformthatgiv