8位加法器程序源代码及仿真波形.docx
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8位加法器程序源代码及仿真波形.docx
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8位加法器程序源代码及仿真波形
1.libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadderis
port(a,b:
instd_logic_vector(15downto0);
sum:
outstd_logic_vector(15downto0));
endadder;
architecturertlofadderis
begin
sum<=a+b;
endrtl;
仿真波形图
2.libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymux4is
port(a,b:
instd_logic_vector(3downto0);
sel:
instd_logic;
y:
outstd_logic_vector(3downto0));
endmux4;
architecturertlofmux4is
begin
process(sel,a,b)
begin
if(sel='0')theny<=a;
elsey<=b;
endif;
endprocess;
endrtl;
仿真波形图
3.libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysevenis
port(input:
instd_logic_vector(2downto0);
a,b,c,d,e,f,g:
outstd_logic);
endseven;
architecturertlofsevenis
begin
process(input)
begin
caseinputis
when"000"=>a<='1';b<='1';c<='1';d<='1';e<='1';f<='1';g<='0';
when"001"=>a<='0';b<='1';c<='1';d<='0';e<='0';f<='0';g<='0';
when"010"=>a<='1';b<='1';c<='0';d<='1';e<='1';f<='0';g<='1';
when"011"=>a<='1';b<='1';c<='1';d<='1';e<='0';f<='0';g<='1';
when"100"=>a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';
when"101"=>a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';
when"110"=>a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';
when"111"=>a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';
endcase;
endprocess;
endrtl;
仿真波形图
4.libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityshifteris
port(input:
instd_logic_vector(7downto0);
cnt:
instd_logic_vector(1downto0);
result:
outstd_logic_vector(15downto0));
endshifter;
architecturertlofshifteris
begin
process(cnt,input)
begin
casecntis
when"00"=>foriin15downto0loop
ifi>=8thenresult(i)<='0';
elseresult(i)<=input(i);
endif;
endloop;
when"01"=>foriin15downto0loop
ifi>=12ori<=3thenresult(i)<='0';
elseresult(i)<=input(i-4);
endif;
endloop;
when"10"=>foriin15downto0loop
ifi>=8thenresult(i)<=input(i-8);
elseresult(i)<='0';
endif;
endloop;
when"11"=>foriin15downto0loop
ifi>=8thenresult(i)<='0';
elseresult(i)<=input(i);
endif;
endloop;
endcase;
endprocess;
endrtl;
仿真波形图
5.
(1)libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityregais
port(in_reg:
instd_logic_vector(15downto0);
clk:
instd_logic;clr:
instd_logic;clken:
instd_logic;
out_reg:
outstd_logic_vector(15downto0));
endrega;
architecturertlofregais
begin
process(clk,clr,clken)
begin
if(clk'eventandclk='1')then
if(clr='1'andclken='0')thenout_reg<=in_reg;
elseout_reg<="0000000000000000";
endif;
endif;
endprocess;
endrtl;
仿真波形图
5.
(2)libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk:
instd_logic;
clr:
instd_logic;
sum:
outstd_logic_vector(1downto0));
endcounter;
architecturertlofcounteris
begin
process(clk,clr)
variablem:
std_logic_vector(1downto0);
begin
if(clr='0')thenm:
="00";
elsif(clk'eventandclk='1')then
m:
=m+1;
endif;
sum<=m;
endprocess;
endrtl;
仿真波形图
6.
(1)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycontrolis
port(clk,rst,start:
instd_logic;
count:
instd_logic_vector(1downto0);
in_sel,shift:
outstd_logic_vector(1downto0);
state_out:
outstd_logic_vector(2downto0);
done,clken,regclr:
outstd_logic);
endentitycontrol;
architecturertlofcontrolis
typestatesis(idle,lsb,err,mid,msb);
signalcurrent_state,next_state:
states;
begin
reg:
process(rst,clk)is
begin
ifrst='1'then
current_state<=idle;
elsif(clk='1'andclk'event)then
current_state<=next_state;
endif;
endprocessreg;
com:
process(current_state,count,start)is
variablem,n:
std_logic;
variabler:
std_logic_vector(1downto0);
begin
casecurrent_stateis
whenidle=>state_out<="000";
ifstart='1'then
next_state<=lsb;
m:
='0';
clken<='1';n:
='0';
elsenext_state<=idle;
m:
='0';
clken<='1';n:
='1';
endif;
whenlsb=>state_out<="001";
if(start='0'andcount="00")then
next_state<=mid;r:
="00";shift<="00";
m:
='0';
clken<='0';n:
='1';
elsenext_state<=err;
m:
='0';
clken<='1';n:
='1';
endif;
whenmid=>state_out<="010";
if(start='0'andcount="01")then
next_state<=mid;r:
="01";shift<="01";
m:
='0';
clken<='0';n:
='1';
elsif(start='0'andcount="10")then
next_state<=msb;r:
="10";shift<="01";
m:
='0';
clken<='0';n:
='1';
elsenext_state<=err;
m:
='0';
clken<='1';n:
='1';
endif;
whenmsb=>state_out<="011";
if(start='0'andcount="11")then
next_state<=idle;r:
="11";shift<="10";
m:
='1';
clken<='0';n:
='1';
elsenext_state<=err;
m:
='0';
clken<='1';n:
='1';
endif;
whenerr=>state_out<="100";
ifstart='1'then
next_state<=lsb;
m:
='0';
clken<='1';n:
='0';
elsenext_state<=err;
m:
='0';
clken<='1';n:
='1';
endif;
endcase;
done<=m;
regclr<=n;
in_sel<=r;
endprocesscom;
endrtl;
6.
(1)仿真波形图
6.
(2)LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYlpm;
USElpm.all;
ENTITYmult4x4IS
PORT
(
dataa:
INSTD_LOGIC_VECTOR(3DOWNTO0);
datab:
INSTD_LOGIC_VECTOR(3DOWNTO0);
result:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDmult4x4;
ARCHITECTURESYNOFmult4x4IS
SIGNALsub_wire0:
STD_LOGIC_VECTOR(7DOWNTO0);
COMPONENTlpm_mult
GENERIC(
lpm_hint:
STRING;
lpm_representation:
STRING;
lpm_type:
STRING;
lpm_widtha:
NATURAL;
lpm_widthb:
NATURAL;
lpm_widthp:
NATURAL
);
PORT(
dataa:
INSTD_LOGIC_VECTOR(3DOWNTO0);
datab:
INSTD_LOGIC_VECTOR(3DOWNTO0);
result:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDCOMPONENT;
BEGIN
result<=sub_wire0(7DOWNTO0);
lpm_mult_component:
lpm_mult
GENERICMAP(
lpm_hint=>"MAXIMIZE_SPEED=5",
lpm_representation=>"UNSIGNED",
lpm_type=>"LPM_MULT",
lpm_widtha=>4,
lpm_widthb=>4,
lpm_widthp=>8
)
PORTMAP(
dataa=>dataa,
datab=>datab,
result=>sub_wire0
);
ENDSYN;
6.
(2)仿真波形图
6.(3)仿真波形图
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