24毕业设计附录.docx
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24毕业设计附录.docx
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24毕业设计附录
附录
一、预处理
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysigned_bumais
port(X_in:
instd_logic_vector(7downto0);---输入
clk:
instd_logic;--输入信号50MHz
buma:
outstd_logic_vector(7downto0));--补码输出
endsigned_buma;
architecturearcofsigned_bumais
signaltemp:
std_logic_vector(7downto0);--中间信号
signalb:
std_logic;--中间信号
begin
b<=X_in(7);
a:
process(clk)
begin
ifclk'eventandclk='1'then
ifb='1'then
temp<=(X_in(7)&(notX_in(6))&(notX_in(5))&(notX_in(4))&
(notX_in(3))&(notX_in
(2))&(notX_in
(1))&(notX_in(0)))+'1';
else
temp<=X_in;
endif;
endif;
endprocess;
buma<=temp;
endarc;
二、移位寄存器
libraryieee;
useieee.std_logic_1164.all;
entitydelayis--------------延时
port
(X_in:
instd_logic_vector(7downto0);--滤波器输入
clk:
instd_logic;--输入时钟
a0,a1,a2,a3,a4,a5,a6,a7:
bufferstd_logic_vector(7downto0);--寄存器
a8,a9,a10,a11,a12,a13,a14,a15:
bufferstd_logic_vector(7downto0)--寄存器);
enddelay;
architectureoneofdelayis
begin
process(clk)
begin
ifclk'eventandclk='1'then
a15<=a14;
a14<=a13;
a13<=a12;
a12<=a11;
a11<=a10;
a10<=a9;
a9<=a8;
a8<=a7;
a7<=a6;
a6<=a5;
a5<=a4;
a4<=a3;
a3<=a2;
a2<=a1;
a1<=a0;
a0<=X_in;
endif;
endprocess;
endone;
三、加法与地址码形成单元VHDL代码如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
useieee.std_logic_arith.all;--输入预加和地址码产生
entityAddressis
port(
a0,a1,a2,a3,a4,a5,a6,a7:
instd_logic_vector(7downto0);--输入寄存器
a8,a9,a10,a11,a12,a13,a14,a15:
instd_logic_vector(7downto0);--输入寄存器
clk:
instd_logic;--输入时钟
y0,y1,y2,y3,y4,y5,y6,y7,y8:
outstd_logic_vector(7downto0));--地址输出
endAddress;
architecturearcofAddressis
signalb0,b1,b2,b3,b4,b5,b6,b7:
std_logic_vector(8downto0);
begin
b0<=(a0(0)&a0)+(a8(0)&a8);
b1<=(a1(0)'&a1)+(a9(0)&a9);
b2<=(a2(0)&a2)+(a10(0)&a10);
b3<=(a3(0)&a3)+(a11(0)&a11);
b4<=(a4(0)&a4)+(a12(0)&a12);
b5<=(a5(0)&a5)+(a13(0)&a13);
b6<=(a6(0)&a6)+(a14(0)&a14);
b7<=(a7(0)&a7)+(a15(0)&a15);
process(clk)
begin
ifclk'eventandclk='1'then--下面产生的8位位矢量将作为LUT的地址
y0<=b7(0)&b6(0)&b5(0)&b4(0)&b3(0)&b2(0)&b1(0)&b0(0);
y1<=b7
(1)&b6
(1)&b5
(1)&b4
(1)&b3
(1)&b2
(1)&b1
(1)&b0
(1);
y2<=b7
(2)&b6
(2)&b5
(2)&b4
(2)&b3
(2)&b2
(2)&b1
(2)&b0
(2);
y3<=b7(3)&b6(3)&b5(3)&b4(3)&b3(3)&b2(3)&b1(3)&b0(3);
y4<=b7(4)&b6(4)&b5(4)&b4(4)&b3(4)&b2(4)&b1(4)&b0(4);
y5<=b7(5)&b6(5)&b5(5)&b4(5)&b3(5)&b2(5)&b1(5)&b0(5);
y6<=b7(6)&b6(6)&b5(6)&b4(6)&b3(6)&b2(6)&b1(6)&b0(6);
y7<=b7(7)&b6(7)&b5(7)&b4(7)&b3(7)&b2(7)&b1(7)&b0(7);
y8<=b7(8)&b6(8)&b5(8)&b4(8)&b3(8)&b2(8)&b1(8)&b0(8);
endif;
endprocess;
endarc;
四、低4位LTU程序(低通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM1is
functionLUT1(y:
instd_logic_vector(3downto0))
returnstd_logic_vector;
endFIR_ROM1;
packagebodyFIR_ROM1is
functionLUT1(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"52";
when"0010"=>m:
=x"4D";
when"0011"=>m:
=x"9f";
when"0100"=>m:
=x"23";
when"0101"=>m:
=x"75";
when"0110"=>m:
=x"70";
when"0111"=>m:
=x"c2";
when"1000"=>m:
=x"2c";
when"1001"=>m:
=x"7e";
when"1010"=>m:
=x"79";
when"1011"=>m:
=x"4f";
when"1100"=>m:
=x"cb";
when"1101"=>m:
=x"a1";
when"1110"=>m:
=x"9c";
when"1111"=>m:
=x"79";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT1;
endFIR_ROM1;
高四位和低四位LUT输出数据要拼在一起,VHDL代码如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
useieee.std_logic_arith.all;
usework.FIR_ROM1.all;
usework.FIR_ROM2.all;
usework.FIR_ROM3.all;
usework.FIR_ROM4.all;
entityfirromis
port(
ADD0,ADD1,ADD2,ADD3,ADD4:
instd_logic_vector(7downto0);
ADD5,ADD6,ADD7,ADD8:
instd_logic_vector(7downto0);
clk:
instd_logic;--输入时钟50MHz
f0,f1,f2,f3,f4,f5,f6,f7,f8:
outstd_logic_vector(12downto0));
endfirrom;
architecturearcoffirromis
signalm0,m1,m2,m3,m4,m5,m6,m7,m8:
std_logic_vector(11downto0);
signalm00,m11,m22,m33,m44,m55,m66,m77,m88:
std_logic_vector(11downto0);
begin
--下面的语句是把高四位输出和低四位输出拼起来
m0<=LUT2(ADD0(7downto4));
m00<=LUT1(ADD0(3downto0));
m1<=LUT2(ADD1(7downto4));
m11<=LUT1(ADD1(3downto0));
m2<=LUT2(ADD2(7downto4));
m22<=LUT1(ADD2(3downto0));
m3<=LUT2(ADD3(7downto4));
m33<=LUT1(ADD3(3downto0));
m4<=LUT2(ADD4(7downto4));
m44<=LUT1(ADD4(3downto0));
m5<=LUT2(ADD5(7downto4));
m55<=LUT1(ADD5(3downto0));
m6<=LUT2(ADD6(7downto4));
m66<=LUT1(ADD6(3downto0));
m7<=LUT2(ADD7(7downto4));
m77<=LUT1(ADD7(3downto0));
m8<=LUT2BU(ADD8(7downto4));
m88<=LUT1BU(ADD8(3downto0));
process(clk)
begin
ifclk'eventandclk='1'then
f0<=(m0(11)&m0)+(m00(11)&m00);f1<=(m1(11)&m1)+(m11(11)&m11);
f2<=(m2(11)&m2)+(m22(11)&m22);f3<=(m3(11)&m3)+(m33(11)&m33);
f4<=(m4(11)&m4)+(m44(11)&m44);f5<=(m5(11)&m5)+(m55(11)&m55);
f6<=(m6(11)&m6)+(m66(11)&m66);f7<=(m7(11)&m7)+(m77(11)&m77);
f8<=(m8(11)&m8)+(m88(11)&m88);
endif;
endprocess;
endarc;
--低四位补码(低通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM2is--程序包
functionLUT1BU(y:
instd_logic_vector(3downto0))--函数体
returnstd_logic_vector;
endFIR_ROM2;
packagebodyFIR_ROM2is
functionLUT1BU(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"fae";
when"0010"=>m:
=x"fb3";
when"0011"=>m:
=x"061";
when"0100"=>m:
=x"fdd";
when"0101"=>m:
=x"f58";
when"0110"=>m:
=x"f5d";
when"0111"=>m:
=x"f0b";
when"1000"=>m:
=x"fd4";
when"1001"=>m:
=x"f82";
when"1010"=>m:
=x"f87";
when"1011"=>m:
=x"fb1";
when"1100"=>m:
=x"f35";
when"1101"=>m:
=x"f5f";
when"1110"=>m:
=x"f64";
when"1111"=>m:
=x"f12";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT1BU;
endFIR_ROM2;
-----高四位(低通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM3is
functionLUT2(y:
instd_logic_vector(3downto0))
returnstd_logic_vector;
endFIR_ROM3;
packagebodyFIR_ROM3is
functionLUT2(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"095";
when"0010"=>m:
=x"103";
when"0011"=>m:
=x"198";
when"0100"=>m:
=x"15f";
when"0101"=>m:
=x"1f4";
when"0110"=>m:
=x"262";
when"0111"=>m:
=x"1f7";
when"1000"=>m:
=x"193";
when"1001"=>m:
=x"228";
when"1010"=>m:
=x"296";
when"1011"=>m:
=x"2f2";
when"1100"=>m:
=x"22b";
when"1101"=>m:
=x"387";
when"1110"=>m:
=x"2f5";
when"1111"=>m:
=x"38a";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT2;
endFIR_ROM3;
--高四位补码(低通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM4is
functionLUT2BU(y:
instd_logic_vector(3downto0))
returnstd_logic_vector;
endFIR_ROM4;
packagebodyFIR_ROM4is
functionLUT2BU(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"f6b";
when"0010"=>m:
=x"efd";
when"0011"=>m:
=x"e68";
when"0100"=>m:
=x"ea1";
when"0101"=>m:
=x"e0c";
when"0110"=>m:
=x"d9e";
when"0111"=>m:
=x"d09";
when"1000"=>m:
=x"e6d";
when"1001"=>m:
=x"dd8";
when"1010"=>m:
=x"d6a";
when"1011"=>m:
=x"d0e";
when"1100"=>m:
=x"cd5";
when"1101"=>m:
=x"c79";
when"1110"=>m:
=x"c6b";
when"1111"=>m:
=x"b76";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT2BU;
endFIR_ROM4;
五、低4位LTU程序(带通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM1is
functionLUT1(y:
instd_logic_vector(3downto0))
returnstd_logic_vector;
endFIR_ROM1;
packagebodyFIR_ROM1is
functionLUT1(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"5";
when"0010"=>m:
=x"14";
when"0011"=>m:
=x"19";
when"0100"=>m:
=x"40";
when"0101"=>m:
=x"45";
when"0110"=>m:
=x"54";
when"0111"=>m:
=x"59";
when"1000"=>m:
=x"80";
when"1001"=>m:
=x"85";
when"1010"=>m:
=x"94";
when"1011"=>m:
=x"c0";
when"1100"=>m:
=x"99";
when"1101"=>m:
=x"c5";
when"1110"=>m:
=x"d4";
when"1111"=>m:
=x"d9";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT1;
endFIR_ROM1;
--低四位补码(带通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM2is--程序包
functionLUT1BU(y:
instd_logic_vector(3downto0))--函数体
returnstd_logic_vector;
endFIR_ROM2;
packagebodyFIR_ROM2is
functionLUT1BU(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"fae";
when"0010"=>m:
=x"fb3";
when"0011"=>m:
=x"061";
when"0100"=>m:
=x"fdd";
when"0101"=>m:
=x"f58";
when"0110"=>m:
=x"f5d";
when"0111"=>m:
=x"f0b";
when"1000"=>m:
=x"fd4";
when"1001"=>m:
=x"f82";
when"1010"=>m:
=x"f87";
when"1011"=>m:
=x"fb1";
when"1100"=>m:
=x"f35";
when"1101"=>m:
=x"f5f";
when"1110"=>m:
=x"f64";
when"1111"=>m:
=x"f12";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT1BU;
endFIR_ROM2;
-----高四位(带通滤波器)
libraryieee;
useieee.std_logic_1164.all;
packageFIR_ROM3is
functionLUT2(y:
instd_logic_vector(3downto0))
returnstd_logic_vector;
endFIR_ROM3;
packagebodyFIR_ROM3is
functionLUT2(y:
instd_logic_vector(3downto0))
returnstd_logic_vectoris
variablem:
std_logic_vector(11downto0);
begin
caseyis
when"0000"=>m:
=x"000";
when"0001"=>m:
=x"cb";
when"0010"=>m:
=x"122";
when"0011"=>m:
=x"1ed";
when"0100"=>m:
=x"161";
when"0101"=>m:
=x"22c";
when"0110"=>m:
=x"283";
when"0111"=>m:
=x"34e";
when"1000"=>m:
=x"18d";
when"1001"=>m:
=x"258";
when"1010"=>m:
=x"2af";
when"1011"=>m:
=x"2ee";
when"1100"=>m:
=x"37a";
when"1101"=>m:
=x"3b9";
when"1110"=>m:
=x"410";
when"1111"=>m:
=x"4db";
whenothers=>m:
=x"000";
endcase;
returnm;
endLUT2;
endFIR_ROM3;
--高四位补码(带通滤波器)
libraryieee
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