外文文献原文基于fpga的逻辑分析仪的设计与实现中英文翻译大学论文.docx
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外文文献原文基于fpga的逻辑分析仪的设计与实现中英文翻译大学论文.docx
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外文文献原文基于fpga的逻辑分析仪的设计与实现中英文翻译大学论文
本科毕业设计(论文)外文翻译
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2017年月日
原文:
ClockBufferBasics
[author]:
Hamilton,Mark1(markh@rennes.ucc.ie);Marnane,WilliamP.1(liam@eleceng.ucc.ie)
[press]:
clockbufferwithFPGA
Clocksarethebasicbuildingblocksforallelectronicstoday.Foreverydatatransitioninasynchronousdigitalsystem,thereisaclockthatcontrolsaregister.MostsystemsuseCrystals,FrequencyTimingGenerators(FTGs),orinexpensiveceramicresonatorstogenerateprecisionclocksfortheirsynchronoussystems.Additionally,clockbuffersareusedtocreatemultiplecopies,multiplyanddivideclockfrequencies,andevenmoveclockedgesforwardsorbackwardintime.Manyclock-bufferingsolutionshavebeencreatedoverthepastfewyearstoaddressthemanychallengesrequiredbytoday’shigh-speedlogicsystems.Someofthesechallengesinclude:
Highoperatingandoutputfrequencies,propagationdelaysfrominputtooutput,outputtooutputskewbetweenpins,cycle-tocycleandlong-termjitter,spreadspectrum,outputdrivestrength,I/Ovoltagestandards,andredundancy.Becauseclocksarethefastestsignalsinasystemandareusuallyundertheheaviestloads,specialconsiderationmustbegivenwhencreatingclockingtrees.Inthischapter,weoutlinethebasicfunctionsofnon-PLLandPLL-basedbuffersandshowhowthesedevicescanbeusedtoaddressthehigh-speedlogicdesignchallenges.
Intoday’stypicalsynchronousdesigns,multipleclocksignalsareoftenneededtodriveavarietyofcomponents.Tocreatetherequirednumberofcopies,aclocktreeisconstructed.Thetreebeginswithaclocksourcesuchasanoscillatororanexternalsignalanddrivesoneormorebuffers.Thenumberofbuffersistypicallydependentonthenumberandplacementofthetargetdevices.
Inyearspast,genericlogiccomponentswereusedasclockbuffers.Thesewereadequateatthetime,buttheydidlittletomaintainthesignalintegrityoftheclock.Infact,theyactuallywereadetrimenttothecircuit.Asclocktreesincreasedinspeedandtimingmarginsreduced,propagationdelayandoutputskewbecameincreasinglyimportant.Inthenextseveralsections,wediscusstheolderdevicesandwhytheyareinadequatetomeettheneedsoftoday’sdesigns.Thedefinitionsofthecommontermsassociatedwithmodernbuffersfollow.Finally,weaddresstheattributesofthemodernclockbufferwithandwithoutaPLL.TheFTGthatisoftenusedasaclocksourceisaspecialtypeofPLLclockbuffer.
◆EarlyBuffers
Aclockbufferisadeviceinwhichtheoutputwaveformfollowstheinputwaveform.Theinputsignalpropagatesthroughthedeviceandisre-drivenbytheoutputbuffers.Hence,suchdeviceshaveapropagationdelayassociatedwiththem.Inaddition,duetodifferencesbetweenthepropagationdelaythroughthedeviceoneachinput-outputpath,skewwillexistbetweentheoutputs.Anexampleofanon-PLLbasedclockbufferisthe74F244thatisavailablefromseveralmanufacturers.Thesedeviceshavebeenavailableformanyyearsandweresuitablefordesignswherefrequencieswerebelow20MHz.Designerswouldbringinaclockandfanitouttomultiplesynchronousdevicesonacircuitcard.Withtheseslowfrequenciesandassociatedrisetimes,designershadsuitablemarginswithwhichtomeetsetupandholdtimesfortheirsynchronousinterfaces.However,thesebuffersarenotoptimalfortoday’shigh-speedclockingrequirements.The74F244suffersfromalongpropagationdelay(3to5ns)andlongoutput-to-outputskewdelays.Non-PLLbasedclockbuffershaveimprovedinrecentyearsandusemoreadvancedI/Odesigntechniquestoimprovetheoutput-to-outputskew.Astheclockperiodgetsshorter,theuncertaintyorskewintheclockdistributionsystembecomesmoreofafactor.Sinceclocksareusedtodrivetheprocessorsandtosynchronizethetransferofdatabetweensystemcomponents,theclockdistributionsystemisanessentialpartofthesystemdesign.Aclockdistributionsystemdesignthatdoesnottakeskewintoconsiderationmayresultinasystemwithdegradedperformanceandreliability.
◆ClockSkew
Skewisthevariationinthearrivaltimeoftwosignalsspecifiedtooccuratthesametime.Skewiscomposedoftheoutputskewofthedrivingdeviceandvariationintheboarddelayscausedbythelayoutvariationoftheboardtraces.Sincetheclocksignaldrivesmanycomponentsofthesystem,andsinceallofthesecomponentsshouldreceivetheirclocksignalatpreciselythesametimeinordertobesynchronized,anyvariationinthearrivaloftheclocksignalatitsdestinationwilldirectlyimpactsystemperformance.Skewdirectlyaffectssystemmarginsbyalteringthearrivalofaclockedge.Becauseelementsinasynchronizedsystemrequireclocksignalstoarriveatthesametime,clockskewreducesthecycletimewithinwhichinformationcanbepassedfromonedevicetothenext.
Assystemspeedsincrease,clockskewbecomesanincreasinglylargeportionofthetotalcycletime.Whencycletimeswere50ns,clockskewwasrarelyadesignpriority.Evenifskewwas20%ofthecycletime,itpresentednoproblem.Ascycletimesdroppedto15nsandless,clockskewrequiresanever-increasingamountofdesignresource.Nowtypically,thesehigh-speedsystemscanhaveonly10%oftheirtimingbudgetdedicatedtoclockskew,soobviously,itmustbereduced.
Therearetwotypesofclockskewthataffectsystemperformance.Theclockdrivercausesintrinsicskewandtheprintedcircuitboard(PCB)layoutanddesignisreferredtoasextrinsicskew.Extrinsicskewandlayoutproceduresforclocktreeswillbediscussedlaterinthisbook.Thevariationoftimeduetoskewisdefinedbythefollowingequation:
tSKEW_INTRINSIC=DeviceInducedSkew
tSKEW_EXTRINSIC=PCB+Layout+OperatingEnvironmentInducedSkew
tSKEW=tSKEW_INTRINSIC+tSKEW_EXTRINSIC
Intrinsicclockskewistheamountofskewcausedbytheclockdriverorbufferbyitself.Boardlayoutoranyotherdesignissues,exceptforthespecificationstatedontheclockdriverdatasheetdonotcauseintrinsicskew.
◆OutputSkew
Outputskew(tSK)isalsoreferredtoaspin-to-pinskew.Outputskewisthedifferencebetweendelaysofanytwooutputsonthesamedeviceatidenticaltransitions.JointElectronicDeviceEngineeringCouncil(JEDEC)definesoutputskewastheskewbetweenspecifiedoutputsofasingledevicewithalldrivinginputsconnectedtogetherandtheoutputsswitchinginthesamedirectionwhiledrivingidenticalspecifiedloads.Figures2.2and2.3showaclockbufferwithcommoninputCindrivingoutputsCo1_1throughCo1_n.Theabsolutemaximumdifferencebetweentherisingedgesoftheoutputswillbespecifiedasoutputskew.Typicaloutputskewintoday’shighperformanceclockbuffersisaround200picoseconds(ps).
◆Part-to-PartSkew
Part-to-partskew(tDSK)isalsoknownaspackageskewanddevice-to-deviceskew.Part-topartskewissimilartooutputskewexceptthatitappliestotwoormoreidenticaldevices.
Part-to-partskewisdefinedasthemagnitudeofthedifferenceinpropagationdelaysbetweenanyspecifiedoutputsoftwoseparatedevicesoperatingatidenticalconditions.Thedevicesmusthavethesameinputsignal,supplyvoltage,ambienttemperature,package,load,environment,etc.Figure2.4illustratestDSKfromtheprecedingexample.
Typicalpart-to-partskewfortoday’shighperformancebuffersisaround500ps.PropagationDelay
Propagationdelay(tPD)isthetimebetweenspecifiedreferencepointsontheinputandoutputvoltagewaveformswiththeoutputchangingfromonedefinedlevel(low)totheother(low).PropagationdelayisillustratedinFigure2.3.Non-PLLbaseddevicesintoday’shighperformancedevicesrangefrom3to7ns.PLL-basedbuffersareabletozerooutthispropagationdelaywiththeaidofPhaseDetectors,LoopFiltersandVoltageControlledOscillators(VCOs).
◆UnevenLoading
Whenusingahigh-speedclockbufferorPLL,caremustbetakentoequallyloadtheoutputsofthedevicetoensurethattightskewtolerancesaremaintained.Inherentineachoutputoftheclockdriverisanoutputimpedancethatismostlyresistiveinnature(alongwithsomeinductanceandcapacitance).Wheneachoftheseresistiveoutputsisequallyloaded,thetightskewspecificationoftheclockdriverispreserved.Iftheloadsbecomeunbalanced,the(RC)timeconstantsofthevariousoutputswouldbedifferent,andtheskewwouldbedirectlyproportionaltothevariationintheloading.
◆InputThresholdVariation
Afterthelowskewclocksignalshavebeendistributed,theclockreceiversmustaccepttheclockinputwithminimalvariations.Iftheinputthresholdlevelsofthereceiversarenotuniform,theclockreceiverswillrespondtotheclocksignalsatdifferenttimescreatingclockskew.Ifoneloaddevicehasathresholdof1.2voltsandanotherloaddevicehasathresholdof1.7voltsandtherisingedgerateis1V/ns,therewillbe500psofskewcausedbythepointatwhichtheloaddeviceswitchesbasedontheinputsignal.Mostmanufacturerscentertheinputthresholdleveloftheirdevicesnear1.5voltsnominalfor(TTL)inputdevices.Thisinputthresholdwillvaryslightlyfrommanufacturertomanufacturerespeciallyasconditions(suchasvoltageandtemperature)change.TheTTLspecificationfortheinputthresholdlevelisguaranteedtobealogichighwhentheinputvoltageisabove2.0voltsandalogiclowwhentheinputvoltagelevelisbelow0.8volts.
Thisleavesa1.2-voltwindowovervoltageandtemperature.ComponentswithComplementaryMetalOxideSemiconductor(CMOS)railswinginputshaveatypicalinputthresholdofVCC/2orabout2.5v
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