期末大作业 数字秒表设计.docx
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期末大作业 数字秒表设计.docx
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期末大作业数字秒表设计
期末大作业数字秒表设计
一、实验任务及要求
设计用于体育比赛用的数字秒表,要求:
1、及时精度大雨1/1000秒,计数器能显示1/1000秒时间,提供给计时器内部定时的始终频率为12MHz;计数器的最长计时时间为1小时,为此需要一个7位的显示器,显示的最长时间为59分59.999秒。
2、设计有复位和起/停开关。
(1)、复位开关用来使计时器清零,并做好计时准备。
(2)、起/停开关的使用方法与传统的机械式计数器相同,即按一下起/停开关,启动计时器开始计时,再按一下起/停开关计时终止。
(3)、复位开关可以在任何情况下使用,即使在计时过程中,只要按一下复位开关,计时进程理科终止,并对计时器清零。
3、采用层次设计方法设计符合上述功能要求的数字秒表。
4、对电路进行功能仿真,通过波形确认电路设计是否正确。
5、完成电路传布设计后,通过实验箱下载验证设计的正确性。
二、数字秒表的电路逻辑图
三、实验内容
1、时序波形图如下:
2、顶层程序框图如下:
3、各功能模块VHDL程序
十分之一秒
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMINSECONDbis
port(clk,clrm,stop:
instd_logic;
secm0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endMINSECONDb;
architectureSECofMINSECONDbis
begin
process(clk,clrm)
variablecnt0:
std_logic_vector(3downto0);
begin
ifclrm='1'then
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifstop='0'then
ifcnt0="1001"then
co<='1';
cnt0:
="0000";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
co<='0';
endif;
elsecnt0:
=cnt0;
endif;
endif;
secm0<=cnt0;
endprocess;
endSEC;
秒
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitySECONDis
port(clk,clr:
instd_logic;
sec1,sec0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endSECOND;
architectureSECofSECONDis
begin
process(clk,clr)
variablecnt1,cnt0:
std_logic_vector(3downto0);
begin
ifclr='1'then
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifcnt1="0101"andcnt0="1000"then
co<='1';
cnt0:
="1001";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
co<='0';
else
cnt0:
="0000";
ifcnt1<"0101"then
cnt1:
=cnt1+1;
else
cnt1:
="0000";
co<='0';
endif;
endif;
endif;
sec1<=cnt1;
sec0<=cnt0;
endprocess;
endSEC;
分
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMINUTEis
port(clk,en,clr:
instd_logic;
min1,min0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endMINUTE;
architectureMINofMINUTEis
begin
process(clk)
variablecnt1,cnt0:
std_logic_vector(3downto0);
begin
ifclr='1'then
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifen='1'then
ifcnt1="0101"andcnt0="1000"then
co<='1';
cnt0:
="1001";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
else
cnt0:
="0000";
ifcnt1<"0101"then
cnt1:
=cnt1+1;
co<='0';
else
cnt1:
="0000";
endif;
endif;
endif;
endif;
min1<=cnt1;
min0<=cnt0;
endprocess;
endMIN;
闹钟
libraryieee;
useieee.std_logic_1164.all;
entitynzis
port(clk:
instd_logic;
time:
instd_logic_vector(23downto0);
h1,h0,m1,m0,s1,s0:
instd_logic_vector(3downto0);
qlk:
outstd_logic);
endnz;
architecturesss_arcofnzis
begin
process(clk)
begin
ifclk'eventandclk='1'then
if(h1=time(23downto20)andh0=time(19downto16)andm1=time(15downto12)and
m0=time(11downto8)ands1=time(7downto4)ands0=time(3downto0))then
qlk<='1';
else
qlk<='0';
endif;
endif;
endprocess;
endsss_arc;
顶层程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitytime2is
port(clk,clr,stop,en,led:
instd_logic;
time:
instd_logic_vector(23downto0);
qlk:
outstd_logic;
hou1,hou0,m1,m0,s1,s0,sm0:
outstd_logic_vector(3downto0));
endtime2;
architecturebavoftime2is
componentMINSECONDb
port(clk,clrm,stop:
instd_logic;
secm0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endcomponent;
componentSECOND
port(clk,clr:
instd_logic;
sec1,sec0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endcomponent;
componentMINUTE
port(clk,en,clr:
instd_logic;
min1,min0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endcomponent;
componentHOUR
port(clk,en,clr,led:
instd_logic;
h1,h0:
outstd_logic_vector(3downto0));
endcomponent;
componentnz
port(clk:
instd_logic;
time:
instd_logic_vector(23downto0);
h1,h0,m1,m0,s1,s0:
instd_logic_vector(3downto0);
qlk:
outstd_logic);endcomponent;
signalc:
std_logic;
signalc1:
std_logic;
signalc2:
std_logic;
signala1,a0,b1,b0,d1,d0,dm0:
std_logic_vector(3downto0);
begin
hou1<=a1;hou0<=a0;m1<=b1;m0<=b0;s1<=d1;s0<=d0;sm0<=dm0;
u1:
MINSECONDb
portmap(clk=>clk,clrm=>clr,stop=>stop,secm0=>dm0,co=>c);
u2:
SECOND
portmap(clk=>c,clr=>clr,sec1=>d1,sec0=>d0,co=>c1);
u3:
MINUTE
portmap(clk=>c1,clr=>clr,min1=>b1,min0=>b0,en=>en,co=>c2);
u4:
HOUR
portmap(clk=>c2,clr=>clr,h1=>a1,h0=>a0,en=>en,led=>led);
u5:
nz
portmap(clk=>clk,h1=>a1,h0=>a0,m1=>b1,m0=>b0,s1=>d1,s0=>d0,qlk=>qlk,
time=>time);
endbav;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMINSECONDbis
port(clk,clrm,stop:
instd_logic;
secm0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endMINSECONDb;
architectureSECofMINSECONDbis
begin
process(clk,clrm)
variablecnt0:
std_logic_vector(3downto0);
begin
ifclrm='1'then
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifstop='0'then
ifcnt0="1001"then
co<='1';
cnt0:
="0000";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
co<='0';
endif;
elsecnt0:
=cnt0;
endif;
endif;
secm0<=cnt0;
endprocess;
endSEC;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitySECONDis
port(clk,clr:
instd_logic;
sec1,sec0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endSECOND;
architectureSECofSECONDis
begin
process(clk,clr)
variablecnt1,cnt0:
std_logic_vector(3downto0);
begin
ifclr='1'then
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifcnt1="0101"andcnt0="1000"then
co<='1';
cnt0:
="1001";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
co<='0';
else
cnt0:
="0000";
ifcnt1<"0101"then
cnt1:
=cnt1+1;
else
cnt1:
="0000";
co<='0';
endif;
endif;
endif;
sec1<=cnt1;
sec0<=cnt0;
endprocess;
endSEC;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMINUTEis
port(clk,en,clr:
instd_logic;
min1,min0:
outstd_logic_vector(3downto0);
co:
outstd_logic);
endMINUTE;
architectureMINofMINUTEis
begin
process(clk)
variablecnt1,cnt0:
std_logic_vector(3downto0);
begin
ifclr='1'then
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifen='1'then
ifcnt1="0101"andcnt0="1000"then
co<='1';
cnt0:
="1001";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
else
cnt0:
="0000";
ifcnt1<"0101"then
cnt1:
=cnt1+1;
co<='0';
else
cnt1:
="0000";
endif;
endif;
endif;
endif;
min1<=cnt1;
min0<=cnt0;
endprocess;
endMIN;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityHOURis
port(clk,en,clr,led:
instd_logic;
h1,h0:
outstd_logic_vector(3downto0));
endHOUR;
architecturehour_arcofHOURis
begin
process(clk)
variablecnt1,cnt0:
std_logic_vector(3downto0);
begin
ifclr='1'then
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifen='1'then
ifled='1'then
ifcnt1="0010"andcnt0="0011"then
cnt1:
="0000";
cnt0:
="0000";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
elsifcnt0="1001"then
cnt1:
=cnt1+1;
cnt0:
="0000";
endif;
else
ifcnt1="0001"andcnt0="0001"then
cnt1:
="0000";
cnt0:
="0000";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
elsifcnt0="1001"then
cnt1:
=cnt1+1;
cnt0:
="0000";
endif;
endif;
endif;
endif;
h1<=cnt1;
h0<=cnt0;
endprocess;
endhour_arc;
libraryieee;
useieee.std_logic_1164.all;
entitynzis
port(clk:
instd_logic;
time:
instd_logic_vector(23downto0);
h1,h0,m1,m0,s1,s0:
instd_logic_vector(3downto0);
qlk:
outstd_logic);
endnz;
architecturesss_arcofnzis
begin
process(clk)
begin
ifclk'eventandclk='1'then
if(h1=time(23downto20)andh0=time(19downto16)andm1=time(15downto12)and
m0=time(11downto8)ands1=time(7downto4)ands0=time(3downto0))then
qlk<='1';
else
qlk<='0';
endif;
endif;
endprocess;
endsss_arc;
4、最终的仿真波形图如下图所示
四、实验结果:
实验成功
五、实验心得:
秒表主要分为分频器、十进制计数器以及秒的十位和分的十位的两个六进制计数器。
设计中首先需要获得比较精确的10Hz的及时脉冲,即周期为1/10秒的即时脉冲。
其次,除了对每个计数器许设计清零信号之外,还需要在十进制技术上设计时钟使能信号,即及时允许信号,一边作为秒表的计时启停控制开关。
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