NXP iMX RT500双核ARM MCU嵌入应用开发方案.docx
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NXP iMX RT500双核ARM MCU嵌入应用开发方案.docx
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NXPiMXRT500双核ARMMCU嵌入应用开发方案
NXPi.MXRT500双核ARMMCU嵌入应用开发方案
NXP公司的i.MXRT500是嵌入应用的双核微控制器(MCU),包括ArmCortex-M33CPU和CadenceRXtensaRFusionF1音频数字信号处理器CPU.Cortex-M33CPU包括两个硬件协处理器,提供增强性能,用于一系列复杂算法和带有LCD接口和MIPIDSIPHY的2D失量GPU.该系列具有丰富的外设和非常低的功耗.器件有多达5MBSRAM,两个FlexSPIs(Octal/QuadSPI接口),每个有32KB缓存,以及一个动态加密,高速USB器件/主+PHY,12位1MSpsADC,模拟比较器,支持8DMIC通路的音频子系统,2DGPU和LCD控制器以及MIPIDSIPHY,SDIO/eMMC;FlexIO;AES/SHA/CryptoM33协处理器和PUF键发生器.控制处理器ArmCortex-M33工作频率高达200MHz,并内置了嵌套中断向量控制器(NVIC),主外接电源1.8V±5%,Vddcore电源从0.6V到1.1V可调,模拟电源1.71-3.6V,五个VDDIO电源为1.71-3.6V,USB电源为3.0-3.6V.主要用在工业领域,智能可穿戴市场以及,智能家庭,物联网(IOT)和玩具与棋类游戏.本文介绍了i.MXRT500主要特性,框图和评估板i.MXRT500EVK(MIMXRT595-EVK)技术和功能指标以及电路图.
Thei.MXRT500isafamilyofdual-coremicrocontrollersforembeddedapplicationsfeaturinganArmCortex-M33CPUcombinedwithaCadenceRXtensaRFusionF1AudioDigitalSignalProcessorCPU.TheCortex-M33includestwohardwarecoprocessorsprovidingenhancedperformanceforanarrayofcomplexalgorithmsalongwitha2DVectorGPUwithLCDInterfaceandMIPIDSIPHY.Thefamilyoffersarichsetofperipheralsandverylowpowerconsumption.Thedevicehasupto5MBSRAM,twoFlexSPIs(Octal/QuadSPIInterfaces)eachwith32KBcache,onewithdynamicdecryption,high-speedUSBdevice/host+PHY,12-bit1MS/sADC,AnalogComparator,
Audiosubsystemssupportingupto8DMICchannels,2DGPUandLCDControllerwithMIPIDSIPHY,SDIO/eMMC;FlexIO;AES/SHA/CryptoM33coprocessorandPUFkeygeneration
i.MXRT500主要特性:
Controlprocessorcore
•ArmCortex-M33processor,runningatfrequenciesofupto200MHz
•ArmTrustZone
•ArmCortex-M33built-inMemoryProtectionUnit(MPU)supportingeightregions
•Single-precisionHardwareFloatingPointUnit(FPU).
•ArmCortex-M33built-inNestedVectoredInterruptController(NVIC).
•Non-maskableInterrupt(NMI)input.
•TwocoprocessorsfortheCortex-M33:
ahardwareacceleratorforfixedandfloatingpointDSPfunctions(PowerQuad)andaCrypto/FFTengine(Casper).
TheDSPcoprocessorusesabankoffourdedicated2KBSRAMs.TheCrypto/FFTengineusesabankoftwo2KBSRAMsthatarealsoAHBaccessiblebytheCPUandtheDMAengine.
•SerialWireDebugwitheightbreakpoints,fourwatchpoints,andadebugtimestampcounter.ItincludesSerialWireOutput(SWO)traceandETMtrace.
•Cortex-M33Systemticktimer
DSPprocessorcore
•CadenceTensilicaFusionF1DSPprocessor,runningatfrequenciesofupto200MHz.
•HardwareFloatingPointUnit.
•SerialWireDebug(sharedwithCortex-M33ControlDomainCPU).
Communicationinterface
•9configurableuniversalserialinterfacemodules(FlexcommInterfaces).EachmodulecontainsanintegratedFIFOandDMAsupport.Eachoftheninemodulescanbeconfiguredas:
•AUSARTwithdedicatedfractionalbaudrategenerationandflow-controlhandshaking
signals.TheUSARTcanoptionallybeclockedat32kHzandoperatedwhenthechipisin
reducedpowermode,usingeitherthe32kHzclockoranexternallysuppliedclock.The
USARTalsoprovidespartialsupportforLIN2.2.
•AnI2C-businterfacewithmultipleaddressrecognition,andamonitormode.Itsupports
400Kb/secFast-modeand1Mb/secFastmodePlus.Italsosupports3.4Mb/sechighspeedwhenoperatinginslavemode.
•AnSPIinterface.
•AnI2S(Inter-ICSound)interfacefordigitalaudioinputoroutput.EachI2Ssupportsuptofourchannel-pairs.
•Twoadditionalhigh-speedSPIinterfacessupporting50MHzoperation
•OneadditionalI2Cinterfacewithopen-drainpads
•TwoI3Cbusinterfaces
•Adigitalmicrophoneinterfacesupportingupto8channelswithassociateddecimatorsandVoice
FiveI/OPowerRails
•Fiveindependentsuppliespoweringdifferentclustersofpinstopermitinterfacingdirectlytooff-chipperipheralsoperatingatdifferentsupplylevels.
On-chipmemory
•Upto5MBofsystemSRAMaccessiblebybothCPUs,bothDMAengines,theGraphicsSubsystemandallotherAHBmasters.
•AdditionalSRAMsforUSBtraffic(16KB),Cortex-M33co-processors(4x2KB),SDIOFIFOs(2x512Bdualport),PUFsecurekeygeneration(2KB),FlexSPIcaches(32KBeach),SmartDMAcommands(32KB),andavarietyofdualandsingleportRAMsfor
graphics.
•16kbitsOTPfuses
•Upto192KBROMmemoryforfactory-programmeddriversandAPIs
•SystembootfromHigh-speedSPI,FlexSPIFlash,HSUSB,I2C,UARToreMMCviaon-chipbootloadersoftwareincludedinROM.FlexSPIbootmodewillincludeanoptionforExecute-in-placestart-upfornonsecureboot.
Digitalperipherals
•TwogeneralpurposeDMAengines,eachwith37channelsandupto27programmablerequest/triggersources.
•CanbeconfiguredsuchthatoneDMAissecureandtheothernon-secureand/oronecanbedesignatedforusebytheM33CPUandtheotherbytheDSP
•SmartDMAControllerwithdedicated32KBcodeRAM
•USBhigh-speedhost/devicecontrollerwithon-chipPHYanddedicatedDMAcontroller.
•TwoFlexSPI(Octal/Quad)Interfacesupto200MHzDDR/SDR(target).32KBcacheswithselectablecachepoliciesbasedonprogrammableaddressregions.OneoftheFlexSPIinterfacewillincludeonthe-flydecryptionforexecute-in-placeandaddressremappingtosupportdual-imageboot.DMAsupported(bothmodules).
•TwoSD/eMMCmemorycardinterfaceswithdedicatedDMAcontrollers.OnesupportseMMC5.0withHS400/DDRoperation.
Analogperipherals
•One12-bitADCwithsamplingratesof1Msamples/secandanenhancedADCcontroller.Itsupportsupto10single-endedchannelsor5differentialchannels.TheADCsupportsDMA.
•Temperaturesensor.
•AnalogcomparatorActivationDetect.OnepairofchannelscanbestreameddirectlytoI2S.TheDMICsupportsDMA.
Timers
•One32-bitSCTimer/PWMmodule(SCT).Multipurposetimerwithextensiveevent-generation,match/compare,andcomplexPWMandoutputcontrolfeatures.
•10general-purpose/PWMoutputs,8generalpurposeinputs
•ItsupportsDMAandcantriggerexternalDMAevents
•Itsupportsfractionalmatchvaluesforhighresolution
•Fivegeneralpurpose,32-bittimer/countermoduleswithPWMcapability
•24-bitmulti-ratetimermodulewith4channelseachcapableofgeneratingrepetitiveinterruptsatdifferent,programmablefrequencies.
•TwoWindowedWatchdogTimers(WDT)withdedicatedwatchdogoscillator(1MHzLPOSC)
•Frequencymeasurementmoduletodeterminethefrequencyofaselectionofon-chiporoff-chipclocksources.
•Real-TimeClock(RTC)withindependentpowersupplyanddedicatedoscillator.Integratedwake-uptimercanbeusedtowakethedeviceupfromlowpowermodes.TheRTCresidesinthe“always-on”voltagedomain.RTCincludeseight32-bitgeneralpurpose
registerswhichcanretaincontentswhenpowerisremovedfromtherestofthechip.
•Ultra-lowpowermicro-tickTimerrunningfromtheWatchdogoscillatorwithcapturecapabilityfortimestamping.Canbeusedtowakeupthedevicefromlow-powermodes.
•64-bitOS/EventTimercommontobothprocessorswithindividualmatch/captureandinterruptgenerationlogic.EnabledonPOR
Clocks
•Crystaloscillatorwithanoperatingrangeof4MHzto26MHz.
•Dualtrimoption:
Internal192/96MHzFROoscillator.Trimmedto1%accuracy.
•FROcapableofbeingtunedusinganaccuratereferenceclock(eg.XTALOsc)to0.1%accuracywith46%dutycycletosupportMIPIPHYandFlexSPI.
•Internal1MHzlow-poweroscillatorwith5%accuracy.ServesasthewatchdogoscillatorandclockfortheOS/EventTimerandtheSystickamongothers.Alsoavailableasthesystemclocktobothdomains.
•32kHzreal-timeclock(RTC)oscillatorthatcanoptionallybeusedasasystemclock.
•MainSystemPLL:
•allowsCPUoperationuptothemaximumratewithouttheneedforahigh-frequencycrystal.
Graphics/Multimedia
•2DVectorGraphicsProcessingUnit,runningatfrequenciesofupto200MHz.
•LCDDisplayInterfacesupportingsmartLCDdisplaysandvideomode.
•MIPIDSIInterfacewithon-chipPHYsupportingtransferratesupto895.1Mbps.
•FlexIOcanbeconfiguredtoprovideaparallelinterfacetoanLCD
I/OPeripherals
•Upto136generalpurposeI/O(GPIO)pinswithconfigurablepull-up/pull-downresistors.Portscanbewrittenaswords,half-words,bytes,orbits.
•Mirrored,secureGPIO0.
•IndividualGPIOpinscanbeusedasedgeandlevelsensitiveinterruptsources,eachwithitsowninterruptvector.
•AllGPIOpinscancontributetooneoftwoganged(OR’d)interruptsfromtheGPIO_HSmodule.
•Agroupofupto7GPIOpins(fromPort0/1)canbeselectedforBooleanpatternmatchingwhichcangenerateinterruptsand/ordrivea“pattern-match”output.
•Adjustableoutputdriverslewrates.
•JTAGboundaryscan
Security
•SecureIsolation:
ProtectionfromsoftwareandremoteattacksusingTrustzoneforarmV8M.HardwareisolationofAESkeys
•SecureBoot:
firmwareinROMprovidingimmutablerootoftrust
•SecureStorage:
PhysicallyUnclonableFunction(PUF)basedkeystore,On-the-fly-AESdecryption(OTFAD)ofoff-chipflashforcodestorage
•SecureDebug:
Certificatebaseddebugauthenticationmechanism
•SecureLoader:
Supportsfirmwareupdatemechanismwithauthenticity(RSAsigned)andconfidentiality(AES-CTRencrypted)protection
•SecureIdentity:
128-bitUniversalUniqueIdentifier(UUID),256-bitCompoundDeviceIdentifier(CDI)perTCGDICEspecification
•CryptographicAccelerators
•Symmetriccryptography(AES)with128/192/256-bitkeystrengthandprotectionagainstSide-channelanalysis(DifferentialPowerAnalysisandTemplateattacks)
•AsymmetriccryptographyaccelerationusingCASPERco-processor
•NISTSP800-90bcompliantTRNGdesignwith512-bitoutputpercall
•HashenginewithSHA-256andSHA1MayberunfromtheFRO,thecrystaloscillatorortheCLKINpin.
•asecond,independentPLLoutputprovidesalternatehigh-frequencyclocksourcefortheDSPCPUiftherequiredfrequencyisdifferentfromthemainsystemclock.(N
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