基于FPGA Verilog RS232串口回环测试例程附源程序仿真源码及测试图片.docx
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基于FPGA Verilog RS232串口回环测试例程附源程序仿真源码及测试图片.docx
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基于FPGAVerilogRS232串口回环测试例程附源程序仿真源码及测试图片
FPGAVerilogRS232串口回环测试
基于FPGAVerilogRS232串口回环测试例程,支持多byte数据传输,附源程序仿真源码及测试图片。
测试基于SSCOM/友善之臂上位机软件测试,测试结果如下图一图二所示。
图一SSCOM
图二
图三连续发送仿真截图
图四连续接收仿真截图
后附verilog源程序代码及testbech仿真例程,注释欠。
重点:
多byte回环测试要点,上位机串口多位数据连续发送停止位和起始位之间无间隔,回环程序在接收和发送都需要具备在停止位后能立马跳转到下一个起始位的能力。
重点关注cnt_bit的处理方式。
附录1顶层例化
uart_txduart_txd(
.clk_50m(sys_clk_50m),
.reset_n(sys_rst_n),
.tx_data(rx_data),
.baud_set(3'd4),
.send_en(rx_done),
.send_done(),
.send_busy(send_busy),
.uart_tx(uart_tx)
);
uart_rxduart_rxd(
.clk_50m(sys_clk_50m),
.reset_n(sys_rst_n),
.rx_data(rx_data),
.baud_set(3'd4),
.rx_done(rx_done),
.rx_busy(rx_busy),
.uart_rx(uart_rx)
);
附录2串口发送源程序
`timescale1ns/1ps
//////////////////////////////////////////////////////////////////////////////////
//Company:
//Engineer:
//
//CreateDate:
2020/06/2109:
45:
23
//DesignName:
//ModuleName:
uart_txd
//ProjectName:
//TargetDevices:
//ToolVersions:
//Description:
//
//Dependencies:
//
//Revision:
//Revision0.01-FileCreated
//AdditionalComments:
//
//////////////////////////////////////////////////////////////////////////////////
moduleuart_txd(
clk_50m,
reset_n,
tx_data,
baud_set,
send_en,
send_done,
send_busy,
uart_tx
);
inputclk_50m;
inputreset_n;
input[7:
0]tx_data;
input[2:
0]baud_set;
inputsend_en;
outputregsend_done;
outputregsend_busy;
outputreguart_tx;
reg[12:
0]cnt;
reg[12:
0]baud_rate_cnt_max;
reg[3:
0]cnt_bit;
reg[7:
0]tx_data_r;
localparambaud_rate_9600=13'd5207;
localparambaud_rate_19200=13'd2603;
localparambaud_rate_38400=13'd1301;
localparambaud_rate_57600=13'd867;
localparambaud_rate_115200=13'd433;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
baud_rate_cnt_max<=baud_rate_115200;
else
case(baud_set)
3'd0:
baud_rate_cnt_max=baud_rate_9600;
3'd1:
baud_rate_cnt_max=baud_rate_19200;
3'd2:
baud_rate_cnt_max=baud_rate_38400;
3'd3:
baud_rate_cnt_max=baud_rate_57600;
3'd4:
baud_rate_cnt_max=baud_rate_115200;
default:
baud_rate_cnt_max=baud_rate_115200;
endcase
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
tx_data_r<=8'd0;
elseif(send_en)
tx_data_r<=tx_data;
else
tx_data_r<=tx_data_r;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
send_busy<=1'b0;
elseif(send_en)
send_busy<=1'b1;
elseif(cnt==baud_rate_cnt_max)begin
if(cnt_bit==4'd10)
send_busy<=1'b0;
else
send_busy<=send_busy;
end
else
send_busy<=send_busy;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
send_done<=1'b0;
elseif(cnt==baud_rate_cnt_max)begin
if(cnt_bit==4'd10)
send_done<=1'b1;
else
send_done<=1'b0;
end
else
send_done<=1'b0;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
cnt<=13'd0;
elseif(send_busy)begin
if(cnt==baud_rate_cnt_max)
cnt<=13'd0;
else
cnt<=cnt+1'b1;
end
else
cnt<=cnt;
/****************************************
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
cnt_bit<=4'd0;
elseif(send_en)//send_enneedstobe1clockhighpulse
cnt_bit<=4'd1;
elseif(cnt==baud_rate_cnt_max)begin
if(cnt_bit==4'd10)
cnt_bit<=4'd0;
else
cnt_bit<=cnt_bit+1'b1;
end
else
cnt_bit<=cnt_bit;
******************************************/
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
cnt_bit<=4'd0;
elseif(send_busy&&(cnt_bit==4'd11))
cnt_bit<=4'd1;
elseif(cnt==1)
cnt_bit<=cnt_bit+1'b1;
else
cnt_bit<=cnt_bit;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)begin
uart_tx<=1'b1;
end
else
case(cnt_bit)
4'd0:
;
4'd1:
uart_tx<=1'b0;//start
4'd2:
uart_tx<=tx_data_r[0];//bit0
4'd3:
uart_tx<=tx_data_r[1];
4'd4:
uart_tx<=tx_data_r[2];
4'd5:
uart_tx<=tx_data_r[3];
4'd6:
uart_tx<=tx_data_r[4];
4'd7:
uart_tx<=tx_data_r[5];
4'd8:
uart_tx<=tx_data_r[6];
4'd9:
uart_tx<=tx_data_r[7];//bit8
4'd10:
uart_tx<=1'b1;//stop
default:
;
endcase
endmodule
附录3串口发送testbench
`timescale1ns/1ps
//////////////////////////////////////////////////////////////////////////////////
//Company:
//Engineer:
//
//CreateDate:
2020/06/2111:
38:
04
//DesignName:
//ModuleName:
uart_txd_tb
//ProjectName:
//TargetDevices:
//ToolVersions:
//Description:
//
//Dependencies:
//
//Revision:
//Revision0.01-FileCreated
//AdditionalComments:
//
//////////////////////////////////////////////////////////////////////////////////
moduleuart_txd_tb();
regclk_50m;
regreset_n;
reg[7:
0]tx_data;
reg[2:
0]baud_set;
regsend_en;
wiresend_done;
wiresend_busy;
wireuart_tx;
parameterCLK_PERIOD=20;
initialclk_50m=0;
always#(CLK_PERIOD/2)clk_50m=~clk_50m;
initialbegin
tx_data=8'h55;
baud_set=4;
reset_n=0;
send_en=0;
#(CLK_PERIOD*100);
reset_n=1;
#CLK_PERIOD;
send_en=1;
#(CLK_PERIOD);
send_en=0;
#(CLK_PERIOD*4340);
send_en=1;
#(CLK_PERIOD);
send_en=0;
#(CLK_PERIOD*4340);
#(CLK_PERIOD*100);
$stop;
end
uart_txduart_txd(
.clk_50m(clk_50m),
.reset_n(reset_n),
.tx_data(tx_data),
.baud_set(baud_set),
.send_en(send_en),
.send_done(send_done),
.send_busy(send_busy),
.uart_tx(uart_tx)
);
endmodule
附录4串口接收源程序
`timescale1ns/1ps
//////////////////////////////////////////////////////////////////////////////////
//Company:
//Engineer:
//
//CreateDate:
2020/06/2115:
30:
30
//DesignName:
//ModuleName:
uart_rxd
//ProjectName:
//TargetDevices:
//ToolVersions:
//Description:
//
//Dependencies:
//
//Revision:
//Revision0.01-FileCreated
//AdditionalComments:
//
//////////////////////////////////////////////////////////////////////////////////
moduleuart_rxd(
clk_50m,
reset_n,
rx_data,
baud_set,
rx_done,
rx_busy,
uart_rx
);
inputclk_50m;
inputreset_n;
outputreg[7:
0]rx_data;
input[2:
0]baud_set;
outputregrx_done;
outputregrx_busy;
inputuart_rx;
reg[12:
0]cnt;
reg[12:
0]baud_rate_cnt_max;
reg[3:
0]cnt_bit;
reguart_rx_r1;
reguart_rx_r2;
wirenedge;
localparambaud_rate_9600=13'd5207;
localparambaud_rate_19200=13'd2603;
localparambaud_rate_38400=13'd1301;
localparambaud_rate_57600=13'd867;
localparambaud_rate_115200=13'd433;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
baud_rate_cnt_max<=baud_rate_115200;
else
case(baud_set)
3'd0:
baud_rate_cnt_max=baud_rate_9600;
3'd1:
baud_rate_cnt_max=baud_rate_19200;
3'd2:
baud_rate_cnt_max=baud_rate_38400;
3'd3:
baud_rate_cnt_max=baud_rate_57600;
3'd4:
baud_rate_cnt_max=baud_rate_115200;
default:
baud_rate_cnt_max=baud_rate_115200;
endcase
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)begin
uart_rx_r1<=8'd0;
uart_rx_r2<=8'd0;
end
elsebegin
uart_rx_r1<=uart_rx;
uart_rx_r2<=uart_rx_r1;
end
assignnedge=uart_rx_r2&(!
uart_rx_r1);
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
rx_busy<=1'b0;
elseif(nedge)
rx_busy<=1'b1;
elseif(cnt==baud_rate_cnt_max)begin
if(cnt_bit==4'd10)
rx_busy<=1'b0;
else
rx_busy<=rx_busy;
end
else
rx_busy<=rx_busy;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
rx_done<=1'b0;
elseif(cnt==baud_rate_cnt_max)begin
if(cnt_bit==4'd10)
rx_done<=1'b1;
else
rx_done<=1'b0;
end
else
rx_done<=1'b0;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
cnt<=13'd0;
elseif(rx_busy)begin
if(cnt==baud_rate_cnt_max)
cnt<=13'd0;
else
cnt<=cnt+1'b1;
end
else
cnt<=cnt;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)
cnt_bit<=4'd1;
elseif(cnt==baud_rate_cnt_max)begin
if(cnt_bit==4'd10)
cnt_bit<=4'd1;
else
cnt_bit<=cnt_bit+1'b1;
end
else
cnt_bit<=cnt_bit;
always@(posedgeclk_50mornegedgereset_n)
if(!
reset_n)begin
rx_data<=8'd0;
end
elseif(cnt==baud_rate_cnt_max/2)
case(cnt_bit)
4'd1:
;//start
4'd2:
rx_data[0]<=uart_rx_r2;//bit0
4'd3:
rx_data[1]<=uart_rx_r2;
4'd4:
rx_data[2]<=uart_rx_r2;
4'd5:
rx_data[3]<=uart_rx_r2;
4'd6:
rx_data[4]<=uart_rx_r2;
4'd7:
rx_data[5]<=uart_rx_r2;
4'd8:
rx_data[6]<=uart_rx_r2;
4'd9:
rx_data[7]<=uart_rx_r2;//bit7
4'd10:
;//stop
default:
;
endcase
else
rx_data<=rx_data;
endmodule
附录5串口接收testbench
`timescale1ns/1ps
//////////////////////////////////////////////////////////////////////////////////
//Company:
//Engineer:
//
//CreateDate:
2020/06/2119:
44:
29
//DesignName:
//ModuleName:
uart_rxd_tb
//ProjectName:
//TargetDevices:
//ToolVersions:
//Description:
//
//Dependencies:
//
//Revision:
//Revision0.01-FileCreated
//AdditionalComments:
//
//////////////////////////////////////////////////////////////////////////////////
moduleuart_rxd_tb();
regclk_50m;
regreset_n;
wire[7:
0]rx_data;
wirerx_done;
wirerx_busy;
reguart_rx;
parameterCLK_PERIOD=20;
initialclk_50m=0;
always#(CLK_PERIOD/2)clk_50m=~clk_50m;
initialbegin
reset_n=0;
uart_rx=1;//idle
#(CLK_PERIOD*100);
reset_n=1;
#CLK_PERIOD;
uart_rx=0;//start
#(CLK_PERIOD*434);
uart_rx=1;//bit0
#(CLK_PERIOD*434);
uart_rx=0;//bit1
#(CLK_PERIOD*434);
uart_rx=1;//bit2
#(CLK_PERIOD*434);
uart_rx=0;//bit3
#(CLK_PERIOD*434);
uart_rx=1;//bit4
#(CLK_PERIOD*434);
uart_rx=0;//bit5
#(CLK_PERIOD*434);
uart_rx=
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