VHDL与数字集成电路设计VHDL7-1.ppt
- 文档编号:2638790
- 上传时间:2022-11-04
- 格式:PPT
- 页数:39
- 大小:3.35MB
VHDL与数字集成电路设计VHDL7-1.ppt
《VHDL与数字集成电路设计VHDL7-1.ppt》由会员分享,可在线阅读,更多相关《VHDL与数字集成电路设计VHDL7-1.ppt(39页珍藏版)》请在冰豆网上搜索。
第七章:
时间考虑第七章:
时间考虑2SynchronousTimingSynchronousTiming3LatchParametersLatchParametersDClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT4RegisterParametersRegisterParametersDClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions5ClockUncertaintiesClockUncertaintiesSourcesofclockuncertainty6ClockNonidealitiesClockNonidealitiesClockskewClockskewSpatialvariationintemporallyequivalentclockedges;deterministic+random,tSKClockjitterClockjitterTemporalvariationsinconsecutiveedgesoftheclocksignal;modulation+randomnoiseCycle-to-cycle(short-term)tJSLongtermtJLVariationofthepulsewidthVariationofthepulsewidthImportantforlevelsensitiveclocking7ClockSkewandJitterClockSkewandJitterBothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemarginClkClktSKtJS8PositiveandNegativeSkewPositiveandNegativeSkew9PositiveSkewPositiveSkewLaunchingedgearrivesbeforethereceivingedge10NegativeSkewNegativeSkewReceivingedgearrivesbeforethelaunchingedge11TimingConstraintsTimingConstraintsMinimumcycletime:
T-=tc-q+tsu+tlogicWorstcaseiswhenreceivingedgearrivesearly(positive)12TimingConstraintsTimingConstraintsHoldtimeconstraint:
t(c-q,cd)+t(logic,cd)thold+WorstcaseiswhenreceivingedgearriveslateRacebetweendataandclock13ImpactofJitterImpactofJitter14LongestLogicPathinLongestLogicPathinEdge-TriggeredSystemsEdge-TriggeredSystemsClkTTSUTClk-QTLMLatestpointoflaunchingEarliestarrivalofnextcycleTJI+15ClockConstraintsinClockConstraintsinEdge-TriggeredSystemsEdge-TriggeredSystemsIflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:
MinimumcycletimeisdeterminedbythemaximumdelaysthroughthelogicTc-q+TLM+TSUTTJI,1TJI,2-ddTc-q+TLM+TSU+dd+2TJITSkewcanbeeitherpositiveornegative16ShortestPathShortestPathClkTClk-QTLmEarliestpointoflaunchingDatamustnotarrivebeforethistimeClkTHNominalclockedge17ClockConstraintsClockConstraintsinEdge-TriggeredSystemsinEdge-TriggeredSystemsMinimumlogicdelayIflaunchingedgeisearlyandreceivingedgeislate:
Tc-q+TLMTJI,1TH+TJI,2+ddTc-q+TLMTH+2TJI+dd18ClockDistributionClockDistributionClockisdistributedinatree-likefashionH-tree19MorerealisticH-treeMorerealisticH-treeRestle9820TheGridSystemTheGridSystemNorc-matchingLargepower2121164Clocking21164Clocking2phasesinglewireclock,distributedglobally2distributeddriverchannelsReducedRCdelay/skewImprovedthermaldistribution3.75nFclockload58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariationtrise=0.35nstskew=150pstcycle=3.3nsClockwaveformClockwaveformLocationofclockLocationofclockdriverondiedriverondiepre-driverfinaldrivers2223ClockSkewinAlphaProcessorClockSkewinAlphaProcessor242Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)Clocking600MHz0.35micronCMOSGlobalclockwaveformGlobalclockwaveform25SynchronousPipelinedDatapathSynchronousPipelinedDatapath26Self-TimedPipelinedDatapathSelf-TimedPipelinedDatapath27Hand-ShakingProtocolHand-ShakingProtocolTwoPhaseHandshake28EventLogicTheMuller-CEventLogicTheMuller-CElementElement292-PhaseHandshakeProtocol30Example:
Self-timedFIFO31PLL-BasedSynchronizationPLL-BasedSynchronization32PLLBlockDiagramPLLBlockDiagram33PhaseDetectorPhaseDetectorOutputbeforefilteringTransfercharacteristic34Phase-FrequencyDetectorPhase-FrequencyDetector35PFDResponsetoFrequencyPFDResponsetoFrequency36ChargePumpChargePump37PLLSimulationPLLSimulation38ClockGenerationusingDLLsClockGenerationusingDLLsPDCPVCONPhase-LockedLoop(VCO-Based)UDfOfREFFilter39DLL-BasedClockDistributionDLL-BasedClockDistribution
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- VHDL 数字 集成电路设计 VHDL7