eda实验报告最终版.docx
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eda实验报告最终版.docx
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eda实验报告最终版
实验一
实验二
1、24进制加法计数器的程序:
LIBRARYIeee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.ALL;
ENTITYcount24IS
PORT(en,clk:
INSTD_LOGIC;
qa:
outSTD_LOGIC_VECTOR(3DOWNTO0);
--个位数计数
qb:
outSTD_LOGIC_VECTOR(1DOWNTO0));
--十位数计数
ENDcount24;
ARCHITECTUREa1OFcount24IS
BEGIN
process(clk)
variabletma:
STD_LOGIC_VECTOR(3DOWNTO0);
variabletmb:
STD_LOGIC_VECTOR(1DOWNTO0);
begin
ifclk'eventandclk='1'then
ifen='1'then
iftma="1001"thentma:
="0000";tmb:
=tmb+1;
Elsiftmb="10"andtma="0011"thentma:
="0000";
tmb:
="00";
elsetma:
=tma+1;
endif;
endif;
endif;
qa<=tma;
qb<=tmb;
endprocess;
ENDa1;
2,60进制的加法器的实验程序
LIBRARY Ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY count60 IS
PORT(en,clk:
IN STD_LOGIC;
qa:
out STD_LOGIC_VECTOR(3 DOWNTO 0);
--个位数计数
qb:
out STD_LOGIC_VECTOR(2 DOWNTO 0));
--十位数计数
END count60;
ARCHITECTURE a1 OF count60 IS
BEGIN
process(clk)
variable tma:
STD_LOGIC_VECTOR(3 DOWNTO 0);
variable tmb:
STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
if clk'event and clk='1' then
if en='1' then
if tma="1001" and tmb="101"
then tmb:
="000";
tma:
="0000" ;
Elsif tma="1001" then tma:
="0000";tmb:
=tmb+1;
else tma:
=tma+1;
end if;
end if;
end if;
qa<=tma;
qb<=tmb;
end process;
END a1;
实验三
9、采用VHDL语言描述以上3-8译码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYs3_8IS
PORT(A:
INSTD_LOGIC_VECTOR(2DOWNTO0);
D:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
END;
ARCHITECTUREoneOFs3_8IS
BEGIN
PROCESS(A)
BEGIN
CASEAIS
WHEN"000"=>D<="00000001";
WHEN"001"=>D<="00000010";
WHEN"010"=>D<="00000100";
WHEN"011"=>D<="00001000";
WHEN"100"=>D<="00010000";
WHEN"101"=>D<="00100000";
WHEN"110"=>D<="01000000";
WHEN"111"=>D<="10000000";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END;
实验四
1、用VHDL语言设计一个四舍五入判别电路,其输入为8421BCD码,要求当输入大于或等于5时,判别电路输出为1,反之为0。
参考电路原理图如图4.1所示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitys4_5is
port(D0,D1,D2,D3:
instd_logic;
OUT1:
outstd_logic);
endentitys4_5;
architectureoneofs4_5is
begin
process(D0,D1,D2,D3)
variablea1:
std_logic;
variableb1:
std_logic;
begin
a1:
=(D0andD2);
b1:
=(D1andD2);
OUT1<=a1ORb1orD3;
endprocess;
endone;
图4.1四舍五入判别参考电路
2、用VHDL语言设计四个开关控制一盏灯的逻辑电路,要求改变任意开关的状态能够引起灯亮灭状态的改变。
(即任一开关的合断改变原来灯亮灭的状态,参考电路原理图如图4.2所示。
)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityk4is
port(k0,k1,k2,k3:
instd_logic;
OUT1:
outstd_logic);
endentityk4;
architectureoneofk4is
begin
process(k0,k1,k2,k3)
variablea1:
std_logic;
variableb1:
std_logic;
begin
a1:
=(k0xork1);
b1:
=(k2xork3);
OUT1<=a1xorb1;
endprocess;
endone;
图4.2灯控参考电路
3、用VHDL语言设计一个优先排队电路(参考电路原理图如图4.3所示),其中:
A=1,最高优先级;B=1,次高优先级;C=1,最低优先级。
要求输出端最多只能有一端为“1”,即只能是优先级较高的输入端所对应的输出端为“1”。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyouxianjiis
port(A:
INSTD_LOGIC_VECTOR(2DOWNTO0);
D:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
endentityyouxianji;
architectureoneofyouxianjiis
begin
process(A)
begin
CASEAIS
WHEN"000"=>D<="000";
WHEN"001"=>D<="001";
WHEN"010"=>D<="010";
WHEN"011"=>D<="010";
WHEN"100"=>D<="100";
WHEN"101"=>D<="100";
WHEN"110"=>D<="100";
WHEN"111"=>D<="100";
WHENOTHERS=>NULL;
ENDCASE;
endprocess;
endone;
图4.3优先排队参考电路
4、自行设计纪录方式,完成实验报告
(1)
(2)
(3)
实验五
RS触发器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysy51is
port(rd,sd:
instd_logic;
q,nq:
outstd_logic);
endentitysy51;
architectureoneofsy51is
begin
process(rd,sd)
variablea1:
std_logic;
variableb1:
std_logic;
begin
a1:
=not(sdandb1);
b1:
=not(rdanda1);
q<=a1;
nq<=b1;
endprocess;
endone;
实验六
实验七
实验八
实验九
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysecondis
port(
CLK:
instd_logic;
RESET:
instd_logic;
A:
outstd_logic_vector(3downto0);
B:
outstd_logic_vector(3downto0);
CKMIN:
outstd_logic
);
endsecond;
architecturetransofsecondis
signalA_xhdl0:
std_logic_vector(3downto0);
signalB_xhdl1:
std_logic_vector(3downto0);
begin
--Drivereferencedoutputs
A<=A_xhdl0;
B<=B_xhdl1;
process(CLK,RESET)
begin
if(RESET='1')then
A_xhdl0<="0000";B_xhdl1<="0000";
elsif(CLK'eventandCLK='1')then
if(A_xhdl0="1001"andB_xhdl1="0101")then
A_xhdl0<="0000";B_xhdl1<="0000";
elsif(A_xhdl0="1001")then
A_xhdl0<="0000";
B_xhdl1<=B_xhdl1+"0001";
else
A_xhdl0<=A_xhdl0+"0001";
endif;
endif;
endprocess;
process(CLK,RESET)
begin
if(RESET='1')then
CKMIN<='0';
elsif(CLK'eventandCLK='1')then
if(A_xhdl0="1001"andB_xhdl1="0101")then
CKMIN<='1';
else
CKMIN<='0';
endif;
endif;
endprocess;
endtrans;
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_unsigned.all;
ENTITYminuteIS
PORT(
CKMIN:
INSTD_LOGIC;
RESET:
INSTD_LOGIC;
SETMIN:
INSTD_LOGIC;
A:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
B:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CKHOUR:
OUTSTD_LOGIC
);
ENDminute;
ARCHITECTUREtransOFminuteIS
SIGNALc:
STD_LOGIC;
SIGNALA_xhdl0:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALB_xhdl1:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
--Drivereferencedoutputs
A<=A_xhdl0;
B<=B_xhdl1;
c<=CKMINXORSETMIN;
PROCESS(c,RESET)
BEGIN
IF(RESET='1')THEN
A_xhdl0<="0000";B_xhdl1<="0000";
ELSIF(c'EVENTANDc='1')THEN
IF(A_xhdl0="1001"ANDB_xhdl1="0101")THEN
A_xhdl0<="0000";B_xhdl1<="0000";
ELSIF(A_xhdl0="1001")THEN
A_xhdl0<="0000";
B_xhdl1<=B_xhdl1+"0001";
ELSE
A_xhdl0<=A_xhdl0+"0001";
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(c,RESET)
BEGIN
IF(RESET='1')THEN
CKHOUR<='0';
ELSIF(c'EVENTANDc='1')THEN
IF(A_xhdl0="1001"ANDB_xhdl1="0101")THEN
CKHOUR<='1';
ELSE
CKHOUR<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDtrans;
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_unsigned.all;
ENTITYhourIS
PORT(
CKHOUR:
INSTD_LOGIC;
RESET:
INSTD_LOGIC;
SETHOUR:
INSTD_LOGIC;
A:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
B:
OUTSTD_LOGIC_VECTOR(1DOWNTO0)
);
ENDhour;
ARCHITECTUREtransOFhourIS
SIGNALc:
STD_LOGIC;
SIGNALA_xhdl0:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALB_xhdl1:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
--Drivereferencedoutputs
A<=A_xhdl0;
B<=B_xhdl1;
c<=CKHOURXORSETHOUR;
PROCESS(RESET,c)
BEGIN
IF(RESET='1')THEN
A_xhdl0<="0000";B_xhdl1<="00";
ELSIF(c'EVENTANDc='1')THEN
IF(A_xhdl0="0011"ANDB_xhdl1="10")THEN
A_xhdl0<="0000";B_xhdl1<="00";
ELSIF(A_xhdl0="1001")THEN
A_xhdl0<="0000";
B_xhdl1<=B_xhdl1+"01";
ELSE
A_xhdl0<=A_xhdl0+"0001";
ENDIF;
ENDIF;
ENDPROCESS;
ENDtrans;
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYdeledIS
PORT(
NUM:
INSTD_LOGIC_VECTOR(3DOWNTO0);
A:
OUTSTD_LOGIC;
B:
OUTSTD_LOGIC;
C:
OUTSTD_LOGIC;
D:
OUTSTD_LOGIC;
E:
OUTSTD_LOGIC;
F:
OUTSTD_LOGIC;
G:
OUTSTD_LOGIC
);
ENDdeled;
ARCHITECTUREtransOFdeledIS
SIGNALxhdl0:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
(G,F,E,D,C,B,A)<=xhdl0;
PROCESS(NUM)
BEGIN
CASENUMIS
WHEN"0000"=>
xhdl0<="0111111";
WHEN"0001"=>
xhdl0<="0000110";
WHEN"0010"=>
xhdl0<="1011011";
WHEN"0011"=>
xhdl0<="1001111";
WHEN"0100"=>
xhdl0<="1100110";
WHEN"0101"=>
xhdl0<="1101101";
WHEN"0110"=>
xhdl0<="1111101";
WHEN"0111"=>
xhdl0<="0000111";
WHEN"1000"=>
xhdl0<="1111111";
WHEN"1001"=>
xhdl0<="1101111";
WHEN"1010"=>
xhdl0<="1000000";
WHEN"1011"=>
xhdl0<="1111100";
WHEN"1100"=>
xhdl0<="0111001";
WHEN"1101"=>
xhdl0<="1011110";
WHEN"1110"=>
xhdl0<="1111001";
WHEN"1111"=>
xhdl0<="1110001";
WHENOTHERS=>
xhdl0<="XXXXXXX";
ENDCASE;
ENDPROCESS;
ENDtrans;
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