EDA技术.docx
- 文档编号:26043091
- 上传时间:2023-06-17
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- 页数:28
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EDA技术.docx
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EDA技术
原理图
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYERIS
PORT(a,b:
INBIT;
s:
INBIT;
y:
OUTBIT);
ENDENTITYER;
ARCHITECTUREoneOFERIS
BEGIN
y<=aWHENs='0'ELSE
b;
ENDARCHITECTUREone;
2选1数据选择器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYBMQIS
PORT(x,y:
INSTD_LOGIC_VECTOR(3DOWNTO0);
s:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDBMQ;
ARCHITECTUREstrucOFBMQIS
BEGIN
PROCESS(x,y)
VARIABLExy:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
xy:
=x&y;
CASExyIS
WHENB"11101110"=>S<=B"0000";
WHENB"11101101"=>S<=B"0001";
WHENB"11101011"=>S<=B"0010";
WHENB"11100111"=>S<=B"0011";
WHENB"11011110"=>S<=B"0100";
WHENB"11011101"=>S<=B"0101";
WHENB"11011011"=>S<=B"0110";
WHENB"11010111"=>S<=B"0111";
WHENB"10111110"=>S<=B"1000";
WHENB"10111101"=>S<=B"1001";
WHENB"10111011"=>S<=B"1010";
WHENB"10110111"=>S<=B"1011";
WHENB"01111110"=>S<=B"1100";
WHENB"01111101"=>S<=B"1101";
WHENB"01111011"=>S<=B"1110";
WHENB"01110111"=>S<=B"1111";
WHENOTHERS=>S<=B"0000";
ENDCASE;
ENDPROCESS;
ENDstruc;
编码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYymqIS
PORT(bcd:
INSTD_LOGIC_VECTOR(3DOWNTO0);
a,b,c,d,e,f,g:
OUTSTD_LOGIC);
ENDymq;
ARCHITECTUREoneOFymqIS
SIGNALdout:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
WITHbcdSELECT
dout<="0111111"WHEN"0000",
"0000110"WHEN"0001",
"1011011"WHEN"0010",
"1001111"WHEN"0011",
"1100110"WHEN"0100",
"1101101"WHEN"0101",
"1111101"WHEN"0110",
"0000111"WHEN"0111",
"1111111"WHEN"1000",
"1101111"WHEN"1001",
"1101111"WHENOTHERS;
g<=dout(6);
f<=dout(5);
e<=dout(4);
d<=dout(3);
c<=dout
(2);
b<=dout
(1);
a<=dout(0);
ENDone;
译码器
译码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSJXZQIS
PORT(s1,s2:
INSTD_LOGIC;
a,b,c,d:
INSTD_LOGIC;
z:
OUTSTD_LOGIC);
ENDSJXZQ;
ARCHITECTUREoneofSJXZQIS
SIGNALs:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
s<=s1&s2;
PROCESS(s1,s2,a,b,c,d)
BEGIN
CASEsIS
WHEN"00"=>z<=a;
WHEN"01"=>z<=b;
WHEN"10"=>z<=c;
WHEN"11"=>z<=d;
WHENOTHERS=>z<='X';
ENDCASE;
ENDPROCESS;
ENDone;
4选1数据选择器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDYS10IS
PORT(cin:
INSTD_LOGIC;
a:
INSTD_LOGIC_VECTOR(7DOWNTO0);
b:
INSTD_LOGIC_VECTOR(7DOWNTO0);
s:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
cout:
OUTSTD_LOGIC);
ENDDYS10;
ARCHITECTUREoneofDYS10IS
COMPONENTDYS
PORT(cin:
INSTD_LOGIC;
a:
INSTD_LOGIC_VECTOR(3DOWNTO0);
b:
INSTD_LOGIC_VECTOR(3DOWNTO0);
s:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
cout:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALcarry_out:
STD_LOGIC;
BEGIN
U1:
DYSPORTMAP(cin=>cin,a=>a(3DOWNTO0),b=>b(3DOWNTO0),
s=>s(3DOWNTO0),cout=>carry_out);
U2:
DYSPORTMAP(cin=>carry_out,a=>a(7DOWNTO4),b=>b(7DOWNTO4),
s=>s(7DOWNTO4),cout=>cout);
ENDone;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDYSIS
PORT(cin:
INSTD_LOGIC;
a:
INSTD_LOGIC_VECTOR(3DOWNTO0);
b:
INSTD_LOGIC_VECTOR(3DOWNTO0);
s:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
cout:
OUTSTD_LOGIC);
ENDDYS;
ARCHITECTUREoneOFDYSIS
SIGNALaa,bb:
STD_LOGIC_VECTOR(4DOWNTO0);
SIGNALsum:
STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
aa<='0'&a;
bb<="0"&b;
sum<=aa+bb+cin;
s<=sum(3DOWNTO0);
cout<=sum(4);
ENDone;
加法器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYCFQIS
PORT(clk,d,clr,pset:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDCFQ;
ARCHITECTUREbehavOFCFQIS
SIGNALq1:
std_LOGIC;
BEGIN
PROCESS(clk,clr)
BEGIN
IF(clr='0')THEN
q1<='0';
ELSIFclk'EVENTANDclk='1'THEN
IF(pset='0')THENq1<='1';
ELSEq1<=d;
ENDIF;
ENDIF;
q<=q1;
ENDPROCESS;
ENDbehav;
触发器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYJCQIS
PORT(clk,ena,clr,oe:
INSTD_LOGIC;
d:
INSTD_LOGIC_VECTOR(7DOWNTO0);
q:
BUFFERSTD_LOGIC_VECTOR(7DOWNTO0));
ENDJCQ;
ARCHITECTUREoneOFJCQIS
SIGNALq_temp:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
PROCESS(clk,clr,ena,oe)
BEGIN
IF(clr='0')THEN
q_temp<="00000000";
ELSIFclk'EVENTANDclk='1'THEN
IF(ena='1')THEN
q_temp<=d;
ENDIF;
ENDIF;
IFoe='1'THENq<="ZZZZZZZZ";
ELSEq<=q_temp;
ENDIF;
ENDPROCESS;
ENDone;
寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYYWJCQIS
PORT(data:
INSTD_LOGIC_VECTOR(7DOWNTO0);
shift_left:
INSTD_LOGIC;
shift_right:
INSTD_LOGIC;
clk:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
mode:
INSTD_LOGIC_VECTOR(1DOWNTO0);
qout:
BUFFERSTD_LOGIC_VECTOR(7DOWNTO0));
ENDYWJCQ;
ARCHITECTUREbehaveOFYWJCQIS
BEGIN
PROCESS
BEGIN
WAITUNTIL(RISING_EDGE(clk));
IF(reset='1')THENqout<="00000000";
ELSE
CASEmodeIS
WHEN"01"=>qout<=shift_right&qout(7DOWNTO1);
WHEN"10"=>qout<=qout(6DOWNTO0)&shift_left;
WHEN"11"=>qout<=data;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDPROCESS;
ENDbehave;
移位寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYclk_divIS
PORT(clk:
INSTD_LOGIC;
clk_div6:
OUTSTD_LOGIC);
ENDclk_div;
ARCHITECTURErtlOFclk_divIS
SIGNALcount:
STD_LOGIC_VECTOR(1DOWNTO0);
SIGNALclk_temp:
STD_LOGIC:
='1';
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENTANDclk='1')THEN
IF(count="10")THEN
count<=(OTHERS=>'0');
clk_temp<=NOTclk_temp;
ELSE
count<=count+1;
ENDIF;
ENDIF;
ENDPROCESS;
clk_div6<=clk_temp;
ENDrtl;六分频
16分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFPQIS
PORT(clk:
INSTD_LOGIC;
clk_div2:
OUTSTD_LOGIC;
clk_div4:
OUTSTD_LOGIC;
clk_div8:
OUTSTD_LOGIC;
clk_div16:
OUTSTD_LOGIC);
ENDFPQ;
ARCHITECTURErtlOFFPQIS
SIGNALcount:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENTANDclk='1')THEN
IF(count="1111")THEN
count<=(OTHERS=>'0');
ELSE
count<=count+1;
ENDIF;
ENDIF;
ENDPROCESS;
clk_div2<=count(0);
clk_div4<=count
(1);
clk_div8<=count
(2);
clk_div16<=count(3);
ENDrtl;
分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSINGTIS
PORT(reset:
INSTD_LOGIC;
clk:
INSTD_LOGIC;
fword:
INSTD_LOGIC_VECTOR(7DOWNTO0);
dout:
OUTSTD_LOGIC_VECTOR(9DOWNTO0));
END;
ARCHITECTUREoneOFSINGTIS
COMPONENTreg32b
PORT(load:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(31DOWNTO0);
dout:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDCOMPONENT;
COMPONENTadder32b
PORT(a:
INSTD_LOGIC_VECTOR(31DOWNTO0);
b:
INSTD_LOGIC_VECTOR(31DOWNTO0);
s:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDCOMPONENT;
COMPONENTsin_rom
PORT(address:
INSTD_LOGIC_VECTOR(9DOWNTO0);
clock:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(9DOWNTO0));
ENDCOMPONENT;
COMPONENTplluIS
PORT(areset:
INSTD_LOGIC;
inclk0:
INSTD_LOGIC;
c0:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALf32b,d32b,din32b:
STD_LOGIC_VECTOR(31DOWNTO0);
SIGNALlocki:
STD_LOGIC;
BEGIN
f32b(27DOWNTO20)<=fword;
f32b(31DOWNTO28)<="0000";
f32b(19DOWNTO0)<="00000000000000000000";
u1:
adder32bPORTMAP(a=>f32b,b=>d32b,s=>din32b);
u2:
reg32bPORTMAP(dout=>d32b,din=>din32b,load=>locki);
u3:
sin_romPORTMAP(address=>d32b(31DOWNTO22),q=>dout,clock=>locki);
u4:
plluPORTMAP(areset=>reset,inclk0=>clk,c0=>locki);
ENDone;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYadder32bIS
PORT(a:
INSTD_LOGIC_VECTOR(31DOWNTO0);
b:
INSTD_LOGIC_VECTOR(31DOWNTO0);
s:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDadder32b;
ARCHITECTUREbehavOFadder32bIS
BEGIN
s<=a+b;
ENDbehav;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYreg32bIS
PORT(load:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(31DOWNTO0);
dout:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDreg32b;
ARCHITECTUREbehavOFreg32bIS
BEGIN
PROCESS(load,din)
BEGIN
IFload'EVENTANDload='1'THEN
dout<=din;
ENDIF;
ENDprocess;
ENDbehav;
基于DSS的正弦信号发生器
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